![](http://datasheet.mmic.net.cn/390000/TVP3010-110_datasheet_16839157/TVP3010-110_5.png)
v
List of Illustrations
Title
Figure
Page
1–1
1–2
Functional Block Diagram
Terminal Assignments
1–3
1–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1
2–2
Dot Clock/VCLK/RCLK/SCLK Relationship
SCLK/VCLK Control Timing
(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency)
SCLK/VCLK Control Timing
(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)
SCLK/VCLK Control Timing
(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)
SCLK/VCLK Control Timing
(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)
Cursor-RAM Organization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Sprite-Origin Settings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual-Cursor Positioning
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
One Possible Custom Cursor Creation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 VGA in the Auxiliary Window
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 Multiple VGA Windows Using Port Select (PSEL)
2–12 Overscan
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–13 Equivalent Circuit of the Current Output (IOG)
2–14 Composite Video Output (With 7.5 IRE, 8-Bit Output)
2–15 Composite Video Output (With 0 IRE, 8-Bit Output)
2–16 Split Shift-Register-Transfer Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9
. . . . . . . . . . . . . . . .
2–3
2–10
. . . . . . . . . . . . . . . . .
2–4
2–10
. . . . . . . . . . . . .
2–5
2–11
2–24
2–25
2–26
2–26
2–29
2–29
2–31
2–34
2–35
2–35
2–36
. . . . . . . . . . . . .
2–6
2–7
2–8
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–2
3–3
MPU Interface Timing
Video Input/Output Timing
SFLAG Timing (When SSRT Function is Enabled)
3–8
3–9
3–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1
A–2
Typical Connection Diagram and Parts
Typical Component Placement With Split-Power Plane
A–3
A–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
B–1
B–2
VCLK and SCLK Phase Relationship (Case 1)
VCLK and SCLK Phase Relationship (Case 2)
B–1
B–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C–1
Little-Endian and Big-Endian Mapping of 8-Bit/Pixel Pseudo-Color Data in
Memory to Monitor Screen
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C–2