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參數(shù)資料
| 型號： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊 |
| 文件頁數(shù)： | 12/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
12
Table 2-3 Pin description for host interface(Cont.)
Signal
Name
100-Pin
Number
I/O
Description
XIOIS16
96
I/O
I/O PORT IS 16 BITS : Memory mode - The PC Card does not have a write
protect switch. This signal is held low after the completion of the reset
initialization sequence.
I/O operation - When the PC Card is configured for I/O operation pin 24 is
used for the -I/O selected is 16-Bit Port (-IOIS16) function. A low signal
indicates that a 16 bit or odd byte only operation can be performed at the
addressed port.
In True IDE mode, this output signal is asserted low when this device is
expecting a word data transfer cycle.
XINPACK
100
O
INPUT PORT ACKNOWLEDGE : This signal is not used in memory mode.
The Input acknowledge signal is asserted by the PC Card when the card is
selected and responding to an I/O read cycle at the address that is on the
address bus. This signal is used by the host to control the enable of any input
data buffers between the PC Card and the CPU.
In True IDE mode, this output signal is not used and should be connected at
the host.
XRDY/
14
O
READY/BUSY : In memory mode, this signal is set high when the PC Card is
ready to accept a new data transfer operation and held low when the card is
busy. The host memory card socket must provide a pull-up resistor. At power
up and at reset, the RDY/-BSY signal is held low (busy) until the PC Card has
completed its power up or reset function. No access of any type should be
made to the PC Card during this time. The RDY/-BSY signal is held high
(disabled from being busy) whenever the following condition is true: The PC
Card has been powered up with +RESET continuously disconnected or
asserted.
I/O operation - After the PC Card has been configured for I/O operation, this
signal is used as Interrupt request. This line is strobed low to generate a
pulse mode interrupt or held low for a level mode interrupt.
In True IDE mode, this signal is the active high Interrupt request to the host.
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