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參數(shù)資料
| 型號： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊 |
| 文件頁數(shù)： | 24/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING
23
3.4 Common Memory Write Timing Specification
Table 3-4 Common Memory Write Timing
Parameter
Symbol
IEEE Symbol
Min ns.
Max ns.
Data Setup before WE
tsu(D-WEH)
tDVWH
80
Data Hold following WE
th(D)
tlWMDX
30
WE Pulse Width
tw(WE)
tWLWH
150
Address Setup Time
tsu(A)
tAVWL
30
CE Setup before WE
tsu(CE)
tELWL
0
Write recovery Time
trec(WE)
tWMAX
30
Address Hold Time
th(A)
tGHAX
20
CE Hold following WE
th(CE)
tGHEH
20
Wait Delay Falling from WE
tv(WT-WE)
tWLWTV
35
WE High from Wait Release
tv(WT)
tWTHWH
0
Wait Width Time
tw(WT)
tWTLWTH
350
Note.
The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Din signifies
data provided by the system to the PC Card. The -WAIT signal may be ignored if the -WE cycle to cycle
time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card
Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in
this specification.
An
-REG
-CE
-WE
-WAIT
Din
th(D)
tsu(A)
tsu(CE)
tv(WT-WE)
tw(WE)
tw(WT)
tsu(D-WEH)
th(A)
th(CE)
tv(WT)
Din Valid
trec(WE)
Figure 3-4 Common Memory Write Timing Diagram
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