參數(shù)資料
型號(hào): UM_S3C49F9X
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: S3C49F9X User’s Manual
中文描述: S3C49F9X用戶手冊(cè)
文件頁(yè)數(shù): 23/74頁(yè)
文件大小: 653K
代理商: UM_S3C49F9X
S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING
22
3.3 Common Memory Read Timing Specification
Table 3-3 Common Memory Read Timing
Parameter
Symbol
IEEE Symbol
Min ns.
Max ns.
Output Enable Access Time
ta(OE)
tGLQV
125
Output Disable Time from OE
tdis(OE)
tGHQZ
100
Address Setup Time
tsu(A)
tAVGL
30
Address Hold Time
th(A)
tGHAX
20
CE Setup before OE
tsu(CE)
tELGL
0
CE Hold following OE
th(CE)
tGHEH
20
Wait Delay Falling from OE
tv(WT-OE)
tGLWTV
35
Data Setup for Wait Release
tv(WT)
tQVWTH
0
Wait Width Time
tw(WT)
tWTLWTH
350
Note.
The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Dout signifies
data provided by the PC Card to the system. The -WAIT signal may be ignored if the -OE cycle to cycle
time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card
Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in
this specification.
An
-REG
-CE
-OE
-WAIT
Dout
tdis(OE)
tsu(A)
tsu(CE)
tv(WT-OE)
ta(OE)
tw(WT)
tv(WT)
th(A)
th(CE)
Figure 3-3 Common Memory Read Timing Diagram
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