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參數(shù)資料
| 型號(hào)： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 20/74頁(yè) |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER INTERFACE BUS TIMMING
3
20
INTERFACE BUS TIMMING
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct
mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the
PCMCIA PC Card Standard. The PC Card conforms to the timing in that reference document.
3.1 Attribute Memory Read Timing Specification
The attribute memory read time is defined as 300ns. Detailed timing specifications are shown in Table 3-
1.
Table 3-1 Attribute Memory Read Timing
300 ns
Parameter
Symbol
IEEE Symbol
Min ns.
Max ns.
Read Cycle Time
tcR
TAVAV
300
Address Access Time
ta(A)
TAVQV
300
Card Enable Access Time
ta(CE)
TELQV
300
Output Enable Access Time
ta(OE)
TGLQV
150
Output Disable Time from CE
tdis(CE)
TEHQZ
100
Output Disable Time from OE
tdis(OE)
TGHQZ
100
Address Setup Time
tsu(A)
TAVWL
30
Output Enable Time from CE
ten(CE)
TELQNZ
5
Output Enable Time from OE
ten(OE)
TGLQNZ
5
Data Valid from Address Change
tv(A)
TAXQX
0
Note.
both the –OE signal & the -WE signal must be de-asserted between consecutive cycle operation.
All times are in nanosecond. Dout signifies data provided by the PC Card to the system. The –CE signal or
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