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參數(shù)資料
| 型號(hào)： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 39/74頁(yè) |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION
38
4.9 ATA Drive Register Set Definition and Protocol
The PC Card can be configured as a high performance I/O device through:
a. Standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary); 170h-177h, 376h-
377h(secondary) with IRQ 14 (or other available IRQ).
b. Any system decoded 16 byte I/O block using any available IRQ.
c. Memory space.
The communication to or from the PC Card is done using the Task File registers which provide all the
necessary registers for control and status information. The PCMCIA interface connects peripherals to the
host using four register mapping methods. The following is a detailed description of these methods:
Table 4-9 I/O Configurations
Standard Configurations
Config Index
I/O or
Memory
Address
Drive #
Description
0 & 8
Memory
0-F, 400-7FF
××
0-
××
F
0
Memory Mapped
1 & 9
I/O
0
I/O Mapped 16 Contiguous Registers
2 & Ah
I/O
1F0-1F7, 3F6-3F7
0
Primary I/O Mapped Drive 0
2 &Ah
I/O
1F0-1F7, 3F6-3F7
1
Primary I/O Mapped Drive 1
3 & Bh
I/O
170-177, 376-377
0
Secondary I/O Mapped Drive 0
3 & Bh
I/O
170-177, 376-377
1
Secondary I/O Mapped Drive 1
Note:
Refer to Section 4.5 for Twin Card implementation.
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