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| 型號： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊 |
| 文件頁數(shù)： | 15/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
15
2.4 Pin Assignment for Flash Memory Interface
Table 2-4 Pin description for Flash memory interface
Signal
Name
100-Pin
Number
I/O
Description
FDB0
FDB1
FDB2
FDB3
FDB4
FDB5
FDB6
FDB7
FDB8
FDB9
FDB10
FDB11
FDB12
FDB13
FDB14
FDB15
50
53
54
55
57
58
59
60
-
-
-
-
-
-
-
-
I/O
FLASH DATA BUS[15:0] : These lines are 16-bit data lines to/from the
flash memory chip.
FRDY0
FRDY1
44
-
I/O
I
FLASH READY 0/1 : The signal is used for indicate to the controller, which
flash memory is ready to accept a command. FDB0 ~ FDB7 are controlled
by FRDY0 signal, FDB8 ~ FDB15 are controlled by FRDY1.
FALE0
FALE1
48
42
I/O
I/O
FLASH ADDRESS LATCH ENABLE 0/1 : When this signal is asserted the
controller can send an address to the flash memory by asserting of FWE
pin. FDB0 ~ FDB7 are controlled by FALE0 signal, FDB8 ~ FDB15 are
controlled by FALE1.
FCLE0
FCLE1
47
41
I/O
I/O
FLASH COMMAND LATCH ENABLE 0/1 : When this signal is asserted, a
command can be to the flash memory. FDB0 ~ FDB7 are controlled by
FCLE0 signal, FDB8 ~ FDB15 are controlled by FCLE1.
FRE0
FRE1
46
40
I/O
I/O
FLASH READ ENABLE 0/1 : This signal is asserted to enable the reading
of data from the flash memory. FDB0 ~ FDB7 are controlled by FRE0
signal, FDB8 ~ FDB15 are controlled by FRE1.
FWE0
FWE1
45
-
I/O
O
FALSH WRITE ENABLE 0/1 : When this signal is asserted , the controller
can write data to the flash memory. FDB0 ~ FDB7 are controlled by FWE0
signal, FDB8 ~ FDB15 are controlled by FWE1.
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