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參數(shù)資料
| 型號(hào)： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊(cè) |
| 文件頁數(shù)： | 13/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
13
Table 2-3 Pin description for host interface(Cont.)
Signal
Name
100-Pin
Number
I/O
Description
XIORD
20
I
I/O READ : This signal is not used in memory mode.
This is an I/O read strobe generated by the host. This signal gates I/O data
onto the bus from the PC Card when the card is configured to use the I/O
interface.
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
XIOWR
19
I
I/O WRITE : This signal is not used in memory mode.
The I/O write strobe pulse is used to clock I/O data on the card data bus into
the PC Card controller registers when the PC Card is configured to use the
I/O interface. The clocking will occur on the negative to positive edge of the
signal (trailing edge).
In True IDE mode, this signal has the same function as in PC Card I/O Mode.
XSTSCHG
97
I/O
STATUS CHANGED : This signal is asserted high as the BVD1 signal since a
battery is not used with this product.
This signal is asserted low to alert the host to changes in the RDY/-BSY and
write protect states, while the I/O interface is configured. Its use is controlled
by the Card config and status
In the True IDE mode, this input / output is the pass diagnostic signal in the
Master / Slave handshake protocol.
XDS
3
I
CARD SELECT : In True IDE mode, this signal is used for configure this
device as a master or slave. When it is grounded , the device is configured as
a master. When this signal is open, the device is configured as a slave.
In I/O and memory mode, this signal is not used.
XRESET
2
I
RESET : When the pin is high, this signal resets the PC Card. The PC Card
is reset only at Power up if this pin is left high or open from power-up. The PC
Card is also reset when the soft reset bit in the Card Configuration Option
Register is set.
In the True IDE mode, this input pin is the active low hardware reset from the
host.
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