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| 型號： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊 |
| 文件頁數(shù)： | 17/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
17
2.5 Pin Assignment for external memory control
Table 2-5 Pin description for external memory interface
Signal
Name
100-Pin
Number
I/O
Description
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
EXTERNAL MEMORY ADDRESS BUS [16:0] : These signals are address
bus to access external memory device as SRAM or ROM.
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
-
-
-
-
-
-
-
-
I/O
EXTERNAL MEMORY DATA BUS [7:0] : These signals are data bus to
access external memory device as SRAM or ROM.
nRCS
-
O
EXTERNAL ROM CHIP SELECT : When this signal is asserted(low active) ,
the controller can access the external ROM device.
nSCS
-
O
EXTERNAL SRAM CHIP SELECT : When this signal is asserted(low active) ,
the controller can access the external SRAM device.
nOE
-
O
OUTPUT ENABLE : This signal is data output enable signal. When an
external memory access for ROM/SRAM occurs, this signal controls the
output enable port of the specific device.
nWE
-
O
WRITE ENABLE : When an external memory device access for SRAM/ROM
occurs, this signal control the write enable port of the specific device.
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