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參數(shù)資料
| 型號： | V850E1 |
| 廠商： | NEC Corp. |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor Core |
| 中文描述： | 32位微處理器內(nèi)核 |
| 文件頁數(shù)： | 103/226頁 |
| 文件大?。?/td> | 1709K |
| 代理商： | V850E1 |
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CHAPTER 9 SHIFTING TO DEBUG MODE
191
User’s Manual U14559EJ3V1UM
Notes 1. The execution address indicates the address of an instruction fetch, and the access address
indicates the address at which an access occurs in accordance with instruction execution.
2. Set as follows.
√:
Set the break conditions.
<0>: Clear all bits to 0.
<1>: It is not necessary to set the conditions, but set all bits to 1 because the initial value is
undefined (bits 31 to 28 of the BPAVn and BPAMn registers are fixed to 0, and cannot
be set to 1).
For an execution trap or for an access trap that targets a 64 MB data area, bits 27 and 26 of
the BPAVn and BPAMn registers are ignored. However, set them to 1 because the initial
value is undefined.
3. Data write: Immediately after execution
Data read: After several instructions are executed (slip)
4. When the MD bit is set to 1, match judgment by the data comparator is ignored. Therefore,
the break latency is accelerated by 1 clock (a break occurs at the MEM stage when MD = 0,
and at the EX stage when MD = 1).
5. Always set to 0 (operation is not guaranteed when set to 1).
6. Set in accordance with the access type (read only, write only, or read/write)
Cautions 1. The match timing of break conditions differs between an execution trap and an
access trap (at the ID stage for an execution trap, and at the MEM stage for an
access trap). Therefore, even if the sequential break mode is set, the V850E1 CPU
may not operate normally when an execution trap occurs after an access trap.
2. In the range break mode, set either the execution trap or access trap to channels 0
and 1.
Remarks
1. n = 0, 1
2. When multiple break conditions are set, the debug mode is entered if at least one of them
is satisfied.
3. Channels 0 and 1 can be linked to perform the following two operations (however,
simultaneous operations are not possible).
(i)
Break by sequential execution (range break mode)
This break is set by setting the SQ bit of the debug interface register (DIR) to 1. The
debug mode is entered only when the break conditions of channels 0 and 1 match in
that order.
(ii) Break by simultaneous execution (range break mode)
This break is set by setting the RE bit of the debug interface register (DIR) to 1. The
debug mode is entered only when the break conditions of channels 0 and 1 match at
the same time.
(b) Break due to misalign access exception occurrence
This break is set by setting the MA bit of the debug interface register (DIR) to 1. The debug mode is
entered when a misalign access occurs during execution of the load and store instructions (independent
of the enable/disable setting of misaligned access to the CPU).
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PDF描述 |
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| V902-FREQ | VCXO, CLOCK, 65 MHz - 200 MHz, LVDS OUTPUT |
| V903-FREQ | VCXO, CLOCK, 200 MHz - 730 MHz, LVDS OUTPUT |
| VB-24STBU | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
| VB-24STCU-5 | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
| VB-24STCU-E | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V850E2FK4-H | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-bit Single-Chip Microcontroller |
| V850E2FL4 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-bit Single-Chip Microcontroller |
| V850E2FL4-H | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-bit Single-Chip Microcontroller |
| V850FX3-CANIT | 制造商:NEC Electronics Corporation 功能描述:STARTER KIT 32BIT CAN |
| V850R3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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