參數(shù)資料
型號(hào)： V850E1
廠商： NEC Corp.
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor Core
中文描述： 32位微處理器內(nèi)核
文件頁(yè)數(shù)： 63/226頁(yè)
文件大?。?/td> 1709K
代理商： V850E1
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User’s Manual U14559EJ3V1UM
155
CHAPTER 6 INTERRUPTS AND EXCEPTIONS
Interrupts are events that occur independently of program execution and are divided into two types: maskable
interrupts and non-maskable interrupts (NMI). In contrast, exceptions are events whose occurrence is dependent on
program execution and are divided into three types: software exceptions, exception traps, and debug traps.
When an interrupt or exception occurs, control is transferred to a handler whose address is determined by the
source of the interrupt or exception. The source of the interrupt/exception is specified by the exception code that is
stored in the exception cause register (ECR). Each handler analyzes the ECR register and performs appropriate
interrupt servicing or exception processing.
The restored PC and restored PSW are written to the status saving
registers (EIPC, EIPSW or FEPC, FEPSW).
To restore execution from interrupt or software exception processing, use the RETI instruction.
To restore
execution from an exception trap or debug trap, use the DBRET instruction. Read the restored PC and restored PSW
from the status saving registers, and transfer control to the restored PC.
Table 6-1. Interrupt/Exception Codes
Interrupt/Exception Source
Name
Trigger
Classification
Exception
Code
Handler
Address
Restored PC
NMI0 input
Interrupt
0010H
00000010H
next PC
Note 2
NMI1 input
Interrupt
0020H
00000020H
next PC
Notes 2, 3
Non-maskable interrupt (NMI)
Note 1
NMI2 input
Note 4
Interrupt
0030H
00000030H
next PC
Notes 2, 3
Maskable interrupt
Note 5
Interrupt
Note 5
Note 6
next PC
Note 2
TRAP0n (n = 0 to FH)
TRAP instruction
Exception
004nH
00000040H
next PC
Software exception
TRAP1n (n = 0 to FH)
TRAP instruction
Exception
005nH
00000050H
next PC
Exception trap (ILGOP)
Illegal instruction
code
Exception
0060H
00000060H
next PC
Note 7
Debug trap
Note 8
DBTRAP
instruction
Note 8
Exception
0060H
00000060H
next PC
Notes 1.
The implemented non-maskable interrupt sources differ depending on the product.
2.
Except when an interrupt is acknowledged during execution of the one of the instructions listed below
(if an interrupt is acknowledged during instruction execution, execution is stopped, and then resumed
after the completion of interrupt servicing. In this case, the address of the interrupted instruction is the
restored PC.).
Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W), divide instructions (DIV, DIVH,
DIVU, DIVHU)
PREPARE, DISPOSE instruction (only if an interrupt is generated before the stack pointer is
updated)
3.
The PC cannot be restored by the RETI instruction. Perform a system reset after interrupt servicing.
4.
Acknowledged even if the NP flag of the PSW is set to 1.
5.
Differs depending on the type of interrupt.
6.
The higher 16 bits are 0000H and the lower 16 bits are the same value as the exception code.
7.
The execution address of the illegal instruction is obtained by “Restored PC – 4”.
8.
Not supported in type C products
Remark
Restored PC: PC value saved to the EIPC or FEPC when interrupt/exception processing is started
next PC:
PC value at which processing is started after interrupt/exception processing
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