參數(shù)資料
型號(hào): XC6SLX100T-2FG484I
廠商: Xilinx Inc
文件頁(yè)數(shù): 44/89頁(yè)
文件大小: 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan® 6 LXT
LAB/CLB數(shù): 7911
邏輯元件/單元數(shù): 101261
RAM 位總計(jì): 4939776
輸入/輸出數(shù): 296
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
49
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 41: CLB Distributed RAM Switching Characteristics (SLICEM Only)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Sequential Delays
TSHCKO
Clock to A – D outputs
1.26
1.55
2.35
ns, Max
Clock to A – D outputs (direct output path)
0.96
1.20
1.87
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS/TDH
AX – DX or AI – DI inputs to CLK
0.59/
0.17
0.73/
0.22
0.73/
0.22
1.17/
0.33
ns, Min
TAS/TAH
Address An inputs to clock for XC devices
0.28/
0.35
0.32/
0.42
0.32/
0.42
0.26/
0.71
ns, Min
Address An inputs to clock for XA and XQ devices
0.28/
0.51
N/A
0.32/
0.51
0.26/
0.71
ns, Min
TWS/TWH
WE input to clock
0.31/
–0.08
0.37/
–0.08
0.37/
–0.08
0.59/
–0.27
ns, Min
TCECK/TCKCE
CE input to CLK
0.31/
–0.08
0.37/
–0.08
0.37/
–0.08
0.59/
–0.27
ns, Min
Table 42: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Sequential Delays
TREG
Clock to A – D outputs
1.35
1.78
2.74
ns, Max
Clock to A – D outputs (direct output path)
1.24
1.65
2.48
ns, Max
Setup and Hold Times Before/After Clock CLK
TWS/TWH
WE input to CLK
0.20/
–0.07
0.24/
–0.07
0.24/
–0.07
0.29/
–0.27
ns, Min
TCECK/TCKCE
CE input to CLK for XC devices
0.30/
0.30
0.30/
0.38
0.30/
0.38
0.82/
–0.41
ns, Min
CE input to CLK for XA and XQ devices
0.32/
0.30
N/A
0.40/
0.38
0.82/
–0.41
ns, Min
TDS/TDH
AX – DX or AI – DI inputs to CLK
0.07/
0.11
0.09/
0.14
0.09/
0.14
0.11/
0.23
ns, Min
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