參數(shù)資料
型號(hào)： XC6SLX100T-2FG484I
廠商： Xilinx Inc
文件頁數(shù)： 84/89頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計(jì)： 4939776
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
85
Revision History
The following table shows the revision history for this document.
Date
Version
Description of Revisions
06/24/09
1.0
Initial Xilinx release.
08/26/09
1.1
Added VFS to Table 1and Table 2. Added RFUSE to Table 2. Added XC6SLX75 and XC6SLX75T to
VBATT and IBATT in Table 1, Table 2, and Table 4. Corrected the quiescent supply current for the
XC6SLX4 in Table 5. Updated Table 11. Removed DVPPIN from Figure 2. Removed FPCIECORE from
Table 24 and added values to FPCIEUSER. Added more networking applications to Table 25. Updated
values for TSUSPENDLOW_AWAKE, TSUSPEND_ENABLE, and TSCP_AWAKE in Table 46. Numerous changes
to Table 47, page 54 including the addition of new values to various specifications, revising the
TSMCKCSO description, and changing the units of TPOR. Also, removed Dynamic Reconfiguration Port
(DRP) for DCM and PLL Before and After DCLK section from Table 47 and updated all the notes. In
Table 52, added to FINMAX, revised FOUTMAX, and removed PLL Maximum Output Frequency for
BUFIO2. Revised values for DCM_DELAY_STEP in Table 54. Updated CLKIN_FREQ_FX values in
01/04/10
1.2
Added -4 speed grade to entire document. Updated speed specification of -4, -3, -2 speed grades to
version 1.03. Added -1L speed grade numbers per speed specification 1.00. Updated TSOL in Table 1.
Added -1L rows for LVCMOS12, LVCMOS15, and LVCMOS18 in Table 9. Revised much of the detail
in GTP Transceiver Specifications in Table 12 through Table 23. Added -2 data to Table 25. Updated
FMAX in Table 44. Updated descriptions for TDNACLKL and TDNACLKH in Table 45 and revised values for
all parameters. Removed TINITADDR from Table 47 and added new data. Updated values in Table 48
through Table 62. Added Table 51 (BUFPLL) and Table 57 (DCM_CLKGEN). Removed
TLOCKMAX note from Table 52. Updated note 3 in Table 53. In Table 79: removed XC6SLX75CSG324
and XC6SLX75TCSG324; added XC6SLX75FG(G)484 and XC6SLX75FG(G)484.
02/22/10
1.3
Production release of XC6SLX16 -2 speed grade devices. The changes to Table 26 and Table 27
includes updating this data sheet to the data in ISE v11.5 software with speed specification v1.06.
Updated maximum of VIN and VTS and note 2 in Table 1. In Table 2, changed VIN, added IIN and note
5, revised notes 1, 6, and 7, and added note 8 to RFUSE. In Table 4, removed previous note 1 and added
data to IRPU, IRPD, and IBATT, changed CIN, added RDT and RIN_TERM, and added note 2 and 3. Updated
VCCO2 in Table 6. Added Table 7 and Table 8. Removed PCI66_3 from Table 9. Updated PCI33_3 and
I2C in Table 9. Updated the description of Table 11. Completely updated Table 25. Updated Table 28
including adding values for PCI33_3. Updated VREF value for HSTL_III_18 in Table 31. Updates
missing VREF values in Table 32. Added Simultaneously Switching Outputs, page 36. Removed TGSRQ
and TRPW from Table 35 and Table 36. Also removed TDOQ from Table 36. Removed TISDO_DO and
note 1 from Table 37. Removed TOSCCK_S and combinatorial section from Table 38. In Table 39,
removed TIODDO_T and added new tap parameters and note 2. In Table 40, Table 41, and Table 42,
made typographical edits and removed notes. Removed clock CLK section in Table 41. Removed clock
CLK section and TREG_MUX and TREG_M31 in Table 42. Added block RAM FMAX values to Table 43.
Updated values and added note 2 to Table 45. Added values to Table 46 and removed note 1.
Numerous changes to Table 47. Completely updated Table 57. Revised data in Table 62. Removed
note 3 from Table 71. Added values to Table 79. Added data to Table 80 and Table 81.
03/10/10
1.4
Production release of XC6SLX45 -2 speed grade devices, which includes changes to Table 26 and
Table 27 updating this data sheet to the data in ISE v11.5 software with speed specification v1.07.
Fixed RIN_TERM description in Table 4. Added PCI66_3 to Table 7 and replaced note 1. Corrected note
1 and the V, Max for TMDS_33 in Table 8. In Table 10, added note 1 to LVPECL_33 and TMDS_33.
Also updated specifications for TMDS_33. Updated the GTP Transceiver Specifications section
including adding values to Table 16, Table 17, and Table 20 through Table 23. Added PCI66_3 back
into Table 9, Table 28, Table 31, Table 32, and Table 34. Updated note 3 on Table 32. In Table 34,
corrected some typographical errors and fixed SSO limits for bank1/3 in FG(G)484 package. Corrected
TOSCKC_OCE in Table 38. In Table 57, updated CLKFX_FREEZE_VAR and
CLKFX_FREEZE_TEMP_SLOPE and added typical values to TCENTER_LOW_SPREAD and
TCENTER_HIGH_SPREAD. Updated and added values to Table 63 through Table 78, and Table 81. In
Table 79, revised the XC6SLX16-CSG324 and the XC6SLX45-CSG484 and FG(G)484 values.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC6SLX100T-2FG676C 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 101261 CELLS 45NM (CMOS) TECHNOLOGY 1 - Trays 制造商:Xilinx 功能描述:IC FPGA 376 I/O 676FCBGA 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 101K 676BGA
XC6SLX100T-2FG676I 功能描述:IC FPGA SPARTAN 6 676FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6SLX100T-2FG900C 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 101261 CELLS 45NM (CMOS) TECHNOLOGY 1 - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 101K 900BGA
XC6SLX100T-2FG900I 功能描述:IC FPGA SPARTAN 6 900FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6SLX100T-2FGG484C 功能描述:IC FPGA SPARTAN 6 101K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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