F
參數(shù)資料
型號： XC6SLX100T-2FG484I
廠商： Xilinx Inc
文件頁數(shù)： 53/89頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計： 4939776
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
57
FINMIN
Minimum Input Clock Frequency
LX devices
19
MHz
LXT devices
19
N/A
MHz
FINJITTER
Maximum Input Clock Period Jitter: 19–200 MHz
All
1 ns Maximum
Maximum Input Clock Period Jitter: > 200 MHz
All
<20% of clock input period Maximum
FINDUTY
Allowable Input Duty Cycle: 19—199 MHz
All
25/75
%
Allowable Input Duty Cycle: 200—299 MHz
All
35/65
%
Allowable Input Duty Cycle: > 300 MHz
All
45/55
%
FVCOMIN
Minimum PLL VCO Frequency
LX devices
400
MHz
LXT devices
400
N/A
MHz
FVCOMAX
Maximum PLL VCO Frequency
LX devices
1080
1050
1000
MHz
LXT devices
1080
1050
1000
N/A
MHz
FBANDWIDTH
Low PLL Bandwidth at Typical(3)
All
1
MHz
High PLL Bandwidth at Typical(3)
All
4
MHz
TSTAPHAOFFSET
Static Phase Offset of the PLL Outputs
All
0.12
0.15
ns
TOUTJITTER
PLL Output Jitter(3)
All
TOUTDUTY
PLL Output Clock Duty Cycle Precision(4)
All
0.15
0.20
0.25
ns
TLOCKMAX
PLL Maximum Lock Time
All
100
s
FOUTMAX
PLL Maximum Output Frequency for BUFGMUX
LX devices
400
375
250
MHz
LXT devices
400
375
N/A
MHz
PLL Maximum Output Frequency for BUFPLL
LX devices
1080
1050
950
500
MHz
LXT devices
1080
1050
950
N/A
MHz
FOUTMIN
PLL Minimum Output Frequency(5)
All
3.125
MHz
TEXTFDVAR
External Clock Feedback Variation: 19–200 MHz
All
1 ns Maximum
External Clock Feedback Variation: > 200 MHz
All
< 20% of clock input period Maximum
RSTMINPULSE
Minimum Reset Pulse Width
All
5
ns
Maximum Frequency at the Phase Frequency Detector LX devices
500
400
300
MHz
LXT devices
500
400
N/A
MHz
FPFDMIN
Minimum Frequency at the Phase Frequency Detector
LX devices
19
MHz
LXT devices
19
N/A
MHz
TFBDELAY
Maximum Delay in the Feedback Path
All
3 ns Max or one CLKIN cycle
Notes:
1.
LXT devices are not available with a -1L speed grade.
2.
Values for this parameter are available in the Clocking Wizard.
3.
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
4.
Includes global clock buffer.
5.
Calculated as FVCO/128 assuming output duty cycle is 50%.
6.
When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector
frequency. FPFDMAX = FCLKFB / CLKFBOUT_MULT
Table 52: PLL Specification (Cont’d)
Symbol
Description
Device(1)
Speed Grade
Units
-3
-3N
-2
-1L
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