參數(shù)資料
型號： XC6SLX100T-2FG484I
廠商： Xilinx Inc
文件頁數(shù)： 54/89頁
文件大小： 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標準包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計： 4939776
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
58
DCM Switching Characteristics
Table 53: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL)(1)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
MinMax
Min
Max
MinMax
Input Frequency Ranges
CLKIN_FREQ_DLL
Frequency of the CLKIN clock
input when the CLKDV output is
not used.
280(3)
280(3)
250(3)
175(3)
MHz
Frequency of the CLKIN clock
input when using the CLKDV
output.
280(3)
280(3)
250(3)
133(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
for
CLKIN_FREQ_DLL < 150 MHz
40
60
40
60
40
60
40
60
%
CLKIN pulse width as a
percentage of the CLKIN period
for
CLKIN_FREQ_DLL > 150 MHz
45
55
45
55
45
55
45
55
%
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
Cycle-to-cycle jitter at the CLKIN
input for
CLKIN_FREQ_DLL < 150 MHz
–
±300
–
±300
–
±300
–
±300
ps
CLKIN_CYC_JITT_DLL_HF
Cycle-to-cycle jitter at the CLKIN
input for
CLKIN_FREQ_DLL > 150 MHz.
–
±150
–
±150
–
±150
–
±150
ps
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input.
–
±1
–
±1
–
±1
–
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of the off-chip
feedback delay from the DCM
output to the CLKFB input.
–±1–
±1
–
±1
–
±1
ns
Notes:
1.
DLL specifications apply when using any of the DLL outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV.
2.
When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies. See Table 55.
3.
The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as
it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the FMAX (see Table 48 and Table 49 for BUFG and
BUFIO2 limits). When used with CLK_FEEDBACK=2X, the input clock frequency matches the frequency for CLK2X, and is limited to
CLKOUT_FREQ_2X.
4.
CLKIN_FREQ_DLL input jitter beyond these limits can cause the DCM to lose LOCK, indicated by the LOCKED output deasserting. The user must
then reset the DCM.
5.
When using both DCMs in a CMT, both DCMs must be LOCKED.
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