參數(shù)資料
型號: XC6SLX100T-2FG484I
廠商: Xilinx Inc
文件頁數(shù): 68/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
標準包裝: 60
系列: Spartan® 6 LXT
LAB/CLB數(shù): 7911
邏輯元件/單元數(shù): 101261
RAM 位總計: 4939776
輸入/輸出數(shù): 296
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應商設備封裝: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
70
Table 68: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-3N
-2
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode
and PLL in DCM2PLL Mode.
TICKOFDCM_PLL
Global Clock and OUTFF with DCM and PLL
XC6SLX4
4.78
N/A
6.32
7.09
ns
XC6SLX9
4.78
5.24
6.32
7.09
ns
XC6SLX16
4.70
5.12
5.94
6.63
ns
XC6SLX25
4.70
5.09
5.92
7.30
ns
XC6SLX25T
4.70
5.09
5.92
N/A
ns
XC6SLX45
4.63
4.98
5.83
7.26
ns
XC6SLX45T
4.63
4.98
5.83
N/A
ns
XC6SLX75
4.68
5.04
5.88
6.90
ns
XC6SLX75T
4.68
5.04
5.88
N/A
ns
XC6SLX100
4.72
5.07
5.92
7.77
ns
XC6SLX100T
4.76
5.07
5.92
N/A
ns
XC6SLX150
4.44
4.73
5.31
6.96
ns
XC6SLX150T
4.44
4.73
5.31
N/A
ns
XA6SLX4
5.07
N/A
6.18
N/A
ns
XA6SLX9
5.07
N/A
6.18
N/A
ns
XA6SLX16
5.22
N/A
5.77
N/A
ns
XA6SLX25
5.01
N/A
5.80
N/A
ns
XA6SLX25T
5.01
N/A
5.90
N/A
ns
XA6SLX45
4.93
N/A
5.67
N/A
ns
XA6SLX45T
4.93
N/A
5.67
N/A
ns
XA6SLX75
4.94
N/A
5.70
N/A
ns
XA6SLX75T
4.94
N/A
5.70
N/A
ns
XA6SLX100
N/A
5.77
N/A
ns
XQ6SLX75
N/A
5.70
6.90
ns
XQ6SLX75T
4.94
N/A
5.70
N/A
ns
XQ6SLX150
N/A
5.31
6.96
ns
XQ6SLX150T
5.02
N/A
5.31
N/A
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2.
DCM and PLL output jitter are already included in the timing calculation.
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