參數(shù)資料
型號： XC6SLX100T-2FG484I
廠商： Xilinx Inc
文件頁數(shù)： 57/89頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計： 4939776
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
60
LOCK_DLL(3)
When using the DLL alone: The time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
CLKIN_FREQ_DLL < 50 MHz.
–
5
–
5
–5–
5
ms
When using the DLL alone: The time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
CLKIN_FREQ_DLL > 50 MHz
–
0.60
–
0.60
–
0.60
–
0.60
ms
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged
over all steps.
10
40
10
40
10
40
10
40
ps
Notes:
1.
The values in this table are based on the operating conditions described in Table 2 and Table 53.
2.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3.
For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute.
4.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of
±(1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns
or 100 ps, the maximum jitter is ±(100 ps + 150 ps) = ±250 ps.
5.
A typical delay step size is 23 ps.
6.
The timing analysis tools use the CLK_FEEDBACK = 1X condition for the CLKIN_CLKFB_PHASE value (reported as phase error). When using
CLK_FEEDBACK = 2X, add 100 ps to the phase error for the CLKIN_CLKFB_PHASE value (as shown in this table).
Table 55: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS)(1)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Input Frequency Ranges(2)
CLKIN_FREQ_FX
Frequency for the CLKIN input. Also
described as FCLKIN.
0.5
375(3)
0.5
0.5
333(3)
0.5
200(3) MHz
Input Clock Jitter Tolerance(4)
CLKIN_CYC_JITT_FX_LF
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency:
FCLKFX < 150 MHz.
–
±300–±300–
±300–±300
ps
CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency:
FCLKFX > 150 MHz.
–
±150–±150–
±150–±150
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input.
–
±1
–
±1
–
±1
–
±1
ns
Notes:
1.
DFS specifications apply when using either of the DFS outputs (CLKFX or CLKFX180).
2.
When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 53.
3.
The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as
it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the FMAX (see Table 48 and Table 49 for BUFG and
BUFIO2 limits).
4.
CLKIN input jitter beyond these limits can cause the DCM to lose LOCK.
Table 54: Switching Characteristics for the Delay-Locked Loop (DLL)(1) (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
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