參數(shù)資料
型號(hào): XC6SLX100T-2FG484I
廠商: Xilinx Inc
文件頁(yè)數(shù): 66/89頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan® 6 LXT
LAB/CLB數(shù): 7911
邏輯元件/單元數(shù): 101261
RAM 位總計(jì): 4939776
輸入/輸出數(shù): 296
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
69
Table 67: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-3N
-2
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode.
TICKOFPLL_0
Global Clock and OUTFF with PLL
XC6SLX4
5.49
N/A
7.44
8.55
ns
XC6SLX9
5.496.297.448.55
ns
XC6SLX16
5.23
5.77
6.79
8.21
ns
XC6SLX25
5.00
5.35
6.10
8.54
ns
XC6SLX25T
5.00
5.35
6.10
N/A
ns
XC6SLX45
5.59
6.03
7.02
8.39
ns
XC6SLX45T
5.59
6.03
7.02
N/A
ns
XC6SLX75
4.96
5.41
6.22
8.32
ns
XC6SLX75T
4.96
5.41
6.22
N/A
ns
XC6SLX100
4.975.426.219.08
ns
XC6SLX100T
5.01
5.42
6.21
N/A
ns
XC6SLX150
4.595.065.868.13
ns
XC6SLX150T
4.59
5.06
5.86
N/A
ns
XA6SLX4
5.79
N/A
7.32
N/A
ns
XA6SLX9
5.79
N/A
7.32
N/A
ns
XA6SLX16
5.56
N/A
6.66
N/A
ns
XA6SLX25
5.40
N/A
5.97
N/A
ns
XA6SLX25T
5.40
N/A
6.07
N/A
ns
XA6SLX45
5.89
N/A
6.90
N/A
ns
XA6SLX45T
5.89
N/A
6.90
N/A
ns
XA6SLX75
5.27
N/A
6.12
N/A
ns
XA6SLX75T
5.27
N/A
6.12
N/A
ns
XA6SLX100
N/A
6.80
N/A
ns
XQ6SLX75
N/A
6.12
8.32
ns
XQ6SLX75T
5.27
N/A
6.12
N/A
ns
XQ6SLX150
N/A
5.88
8.13
ns
XQ6SLX150T
5.21
N/A
5.88
N/A
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2.
PLL output jitter is included in the timing calculation.
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