
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
á
101
the TR byte of the outbound E3 frame. In the sixteenth of a set of 16 E3 Frames, the Transmit DS3/E3 Framer
block will read in the contents of this register, and insert it into the TR byte-field, within the very next outbound
E3 frame.
The contents of this register, along with Tx TTB-1 through Tx TTB-15 are used to transmit 15 ASCII characters
required for the E.164 numbering format.
2.3.6.23
Transmit E3 FA1 Byte Error Mask Register (E3, ITU-T G.832)
This Read/Write bit-field permits the user to insert errors into the Framing Alignment octet, FA1 of each
outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to transmission, the
Transmit DS3/E3 Framer block reads in the FA1 byte, and performs an XOR operation with it and the contents
of this register. The results of this operation are written back into the FA1 octet position, in each outbound E3
frame. Consequently, to insure errors are not injected into the FA1 octet of the outbound E3 frames, the
contents of this register must be set to all “0’s” (the default value).
2.3.6.24
Transmit E3 FA2 Byte Error Mask Register (E3, ITU-T G.832)
This Read/Write bit-field permits the user to insert errors into the Framing Alignment octet, FA2 of each
outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to transmission, the
Transmit DS3/E3 Framer block reads in the FA2 byte, and performs an XOR operation with it and the contents
of this register. The results of this operation are written back into the FA2 octet position, in each outbound E3
frame. Consequently, to insure errors are not injected into the FA2 octet of the outbound E3 frames, the
contents of this register must be set to all "0’s" (the default value).
2.3.6.25
Transmit E3 BIP-8 Error Mask Register (E3, ITU-T G.832)
This Read/Write bit-field permits the user to insert errors into EM (Error Monitor) octet of each outbound E3
frame. The user may wish to do this for equipment testing purposes. Prior to transmission, the Transmit DS3/
E3 Framer block reads in the EM byte, and performs an XOR operation with it and the contents of this register.
The results of this operation are written back into the EM octet position, in each outbound E3 frame.
TxE3 FA1 Error Mask Register (Address = 0x48)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxFA1_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TxE3 FA2 Error Mask Register (Address = 0x49)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxFA2_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TxE3 BIP-8 Error Mask Register (Address = 0x4A)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxBIP-8_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0