XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
á
17
88
RxClk
O
Receive Clock Output Signal for Serial and Nibble/Parallel Data Inter-
face:
The exact behavior of this signal depends upon whether the XRT72L50 is
operating in the Serial or in the Nibble-Parallel-Mode.
Serial Mode Operation:
In the serial mode, this signal is a 44.736MHz clock output signal (for DS3
applications) or 34.368MHz clock output signal (for E3 applications). The
Receive Payload Data Output Interface will update the data via the RxSer out-
put pin, upon the rising edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sam-
ple the data on the RxSer pin, upon the falling edge of this clock signal.
Nibble-Parallel Mode Operation:
In this Nibble-Parallel Mode, the XRT72L50 will derive this clock signal, from
the RxLineClk signal. The XRT72L50 will pulse this clock signal 1176 times
for each inbound DS3 frame (or 1074 times for each inbound E3/ITU-T G.832
frame, or 384 times for each inbound E3/ITU-T G.751 frame). The Receive
Payload Data Output interface will update the data, on the RxNib[3:0] output
pins upon the falling edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sam-
ple the data on the RxNib[3:0] output pins, upon the rising edge of this clock
signal
89
GND
****
Ground
90
RxFrame
O
Receive Boundary of DS3 or E3 Frame Output Indicator:
The exact functionality of this output pin depends upon whether the
XRT72L50 Framer IC is operating in the Serial or Nibble-Parallel Mode.
Serial Mode Operation:
The Receive Section of the XRT72L50 will pulse this output pin "High" (for
one bit-period) when the Receive Payload Data Output Interface block is driv-
ing the very first bit of a given DS3 or E3 frame, onto the RxSer output pin.
Nibble-Parallel Operation:
The Receive Section of the XRT72L50 will pulse this output pin "High" (for
one nibble-period), when the Receive Payload Data Output Interface block is
driving the very first nibble of a given DS3 or E3 frame, onto the RxNib[3:0]
output pins.
91
VDD
****
Power Supply 3.3V + 5%
92
RxOutClk/
RxHDLCDat7
O
Receive Out Clock - Transmit Terminal Interface Clock for Loop-Timing:
This clock signal functions as the Terminal Interface clock source, if the
XRT72L50 Framer IC is operating in the loop-timing mode.
In this mode, the Transmitting Terminal Equipment is expected to input data to
the Framer IC, via the TxSer input pin, upon the rising edge of this clock sig-
nal. The XRT72L50 will use the rising edge of this clock signal to sample the
data at the TxSer input.
This clock signal is a buffered version of the RxLineClk signal.
Receive HDLC Data Output - 7:
This pin contains bit 7 RxHDLC data when the HDLC controller is on.
PIN DESCRIPTION
P
IN
#
P
IN
N
AME
T
YPE
D
ESCRIPTION