
á
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
XIII
XRT72L50 and the Terminal Equipment ...................................................................................................... 434
Figure 198. The XRT72L50 DS3/E3 Framer IC being interfaced to the Receive Section of the Terminal Equipment (Nibble-
Parallel Mode Operation) ............................................................................................................................. 435
6.3.6 Receive Section Interrupt Processing ................................................................................................... 436
Figure 199. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).
436
6.3.6.1 Enabling Receive Section Interrupts ........................................................................................... 437
6.3.6.2 Enabling/Disabling and Servicing Interrupts ............................................................................... 437
7.0 diagnostic operation of the xrt72L50 framer ic .............................................................................. 450
Figure 200. The Framer Local Loop-back Path within the XRT72L50 DS3/E3 Framer IC .......................................... 450
8.0 High Speed HDLC Controller Mode of Operation ........................................................................... 451
8.1 C
ONFIGURING
THE
XRT72L50
TO
OPERATE
IN
THE
H
IGH
S
PEED
HDLC C
ONTROLLER
M
ODE
.............................. 451
8.2 O
PERATING
THE
H
IGH
S
PEED
HDLC C
ONTROLLER
............................................................................................ 452
8.2.1 Operating the Transmit HDLC Controller Block .................................................................................... 452
T
ABLE
89: D
ESCRIPTION
OF
E
ACH
OF
THE
T
RANSMIT
HDLC C
ONTROLLER
P
IN
................................................................ 452
Figure 201. TxHDLC timing for CRC16 ...................................................................................................................... 453
Figure 202. TxHDLC timing for CRC32 ...................................................................................................................... 454
Figure 203. An Outbound HDLC Frame when CRC-32 is selected. .......................................................................... 454
Figure 204. An Outbound HDLC Frame when CRC-16 is selected ........................................................................... 454
8.2.2 Operating the Receive HDLC Controller Block ..................................................................................... 455
8.2.2.1 Receive Payload HDLC Processor ............................................................................................. 455
T
ABLE
90: D
ESCRIPTION
OF
E
ACH
OF
THE
R
ECEIVE
HDLC C
ONTROLLER
P
INS
............................................................... 455
Figure 205. Timing Diagram for RxHDLC Operation .................................................................................................. 456
ORDERING INFORMATION ........................................................................................ 457
PACKAGE DIMENSIONS ............................................................................................ 457
R
EVISION
H
ISTORY
................................................................................................................................ 458