XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
á
55
If this bit-field is set to "0", then the Receive Section (of the channel) is currently not declaring an FERF
condition.
If this bit-field is set to "1", then the Receive Section (of the chip) is currently declaring an FERF condition.
N
OTE
:
For more information on how the Receive Section of the channel declares the FERF condition, refer to
Section 4.3.2.5.4
.
Bit 3 - RxAIC
This Read Only bit-field reflects the value of the AIC bit-field, within the incoming DS3 Frames, as detected by
the Receive DS3/E3 Framer block (within the channel). This bit-field is set to "1" if the incoming frame is
determined to be in the C-bit Parity Format (AIC bit = 1) for at least 63 consecutive frames. This bit-field is set
to "0" if two (2) or more M-frames, out of the last 15 M-frames, contain a "0" in the AIC bit position.
Bits 2:0 - RxFEBE[2:0]
These Read-Only bit-fields reflect the FEBE value within the most recently received DS3 frame.
If these bit-fields are set to "111", then it indicates that the Remote Receiving Terminal is receiving DS3 frames
in an un-erred manner.
If these bit-fields are set to "011", then it indicates that the Remote Receiving Terminal has detected Framing or
Parity bit errors in the DS3 frames that it is receiving.
N
OTE
:
For more information on FEBE (Far-End-Block Error), refer to
Section 4.3.2.5.5
.
2.3.2.10
Receive DS3 Interrupt Enable Register
Bit 7 - CP Bit Error Interrupt Enable
This Read/Write bit-field is used to enable or disable the Detection of CP-Bit Error Interrupt. Setting this bit-
field to “1’ enables this interrupt. Setting this bit-field to “0” disables this interrupt.
N
OTES
:
1.
For more information on the CP-Bit Error Checking/Detection, refer to
Section 4.3.2.6.2
.
2.
This bit-field is only valid if the Channel has been configured to operate in the DS3, C-Bit Parity Framing format.
Bit 6 - LOS Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in LOS condition interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on the LOS Condition, refer to
Section 4.3.2.5.1
.
Bit 5 - AIS Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in AIS condition interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on the AIS Condition, refer to
Section 4.3.2.5.2
.
Bit 4 - Idle Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in Idle condition interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on the Idle Condition, refer to
Section 4.3.2.5.3
.
RxDS3 Interrupt Enable Register (Address = 0x12)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0