XRT75R03D
63
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Channel 2
Interrupt Status
Channel 1
Interrupt Status
Channel 0
Interrupt Status
R/O
0
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
7 - 3
Unused
R/O
0
2
Channel 2
Interrupt
Status
R/O
0
Channel 2 Interrupt Status Bit:
This READ-ONLY bit-field indicates whether or not the XRT75R03D
has a pending Channel 2-related interrupt that is awaiting service.
0 - Indicates that there is NO Channel 2-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel 2-related Interrupt
awaiting service. In this case, the user's Interrupt Service routine
should be written such that the Microprocessor will now proceed to
read out the contents of the Source Level Interrupt Status Register -
Channel 2 (Address Location = 0x12) in order to determine the exact
cause of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0"
until the user has read out the contents of the Source-Level
Interrupt Status Register bit, that corresponds with the
interrupt request.