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| 型號(hào)： | XRT75R03DIVTR-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 92/135頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 帶卷 (TR) |
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XRT75R03D
III
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
REV. 1.0.4
9.2.2 DIGITAL LOOPBACK: ................................................................................................................................................ 88
FIGURE 28. DIGITAL LOOPBACK...................................................................................................................................................... 88
9.2.3 REMOTE LOOPBACK: ............................................................................................................................................... 88
FIGURE 29. REMOTE LOOPBACK .................................................................................................................................................... 88
9.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 89
FIGURE 30. TRANSMIT ALL ONES (TAOS) ...................................................................................................................................... 89
10.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75R03D ...............................................89
10.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .......................... 90
FIGURE 31. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ........ 91
10.2 MAPPING/DE-MAPPING JITTER/WANDER ............................................................................................... 92
10.2.1 HOW DS3 DATA IS MAPPED INTO SONET ........................................................................................................... 92
FIGURE 32. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME .............................................................................................. 93
FIGURE 33. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
94
FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 95
FIGURE 35. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 96
FIGURE 36. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE....................................................................................... 97
FIGURE 37. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE... 98
FIGURE 38. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO
AN
STS-1 SPE .............................................................................................................................................................. 98
10.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ....................................... 99
FIGURE 39. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE ............................ 100
FIGURE 40. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3
SIGNAL THAT HAS A BIT RATE OF
44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL .............................................................. 102
FIGURE 41. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL
THAT HAS A BIT RATE OF
44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL .......................................................................... 103
10.3
JITTER/WANDER DUE TO POINTER ADJUSTMENTS ........................................................................... 103
10.3.1 THE CONCEPT OF AN STS-1 SPE POINTER....................................................................................................... 104
FIGURE 42. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES .................................. 104
FIGURE 43. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION
OF THE
J1 BYTE, DESIGNATED ....................................................................................................................................... 105
FIGURE 44. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2
BYTES
) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME .............................. 105
10.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK .............................................................................. 105
10.3.3 CAUSES OF POINTER ADJUSTMENTS ............................................................................................................... 106
FIGURE 45. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER ........................................................... 107
FIGURE 46. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS
DESIGNATED
................................................................................................................................................................. 108
FIGURE 47. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS
DESIGNATED
................................................................................................................................................................. 109
10.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ........................................................................... 110
10.4 CLOCK GAPPING JITTER ......................................................................................................................... 110
FIGURE 48. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE XRT75R03D IN A SONET DE-SYNC APPLICATION ................. 110
10.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS ........................................................................................................................... 111
TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS 111
10.5.1 DS3 DE-MAPPING JITTER..................................................................................................................................... 112
10.5.2 SINGLE POINTER ADJUSTMENT ......................................................................................................................... 112
FIGURE 49. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO ....................................................................................... 112
10.5.3 POINTER BURST.................................................................................................................................................... 113
FIGURE 50. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ................................................................................... 113
10.5.4 PHASE TRANSIENTS............................................................................................................................................. 113
FIGURE 51. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO ................................................................... 114
10.5.5 87-3 PATTERN ........................................................................................................................................................ 114
FIGURE 52. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN ........................................................... 114
10.5.6 87-3 ADD ................................................................................................................................................................. 115
FIGURE 53. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN .............................................................................. 115
10.5.7 87-3 CANCEL.......................................................................................................................................................... 115
FIGURE 54. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO.............................................................................. 116
10.5.8 CONTINUOUS PATTERN ....................................................................................................................................... 116
FIGURE 55. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO .............................................................. 116
10.5.9
CONTINUOUS ADD ............................................................................................................................................... 117
FIGURE 56. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO....................................................................... 117
10.5.10 CONTINUOUS CANCEL ....................................................................................................................................... 117
FIGURE 57. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO ................................................................. 118
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| VE-J3K-MX-S | CONVERTER MOD DC/DC 40V 75W |
| VE-J3B-MX-S | CONVERTER MOD DC/DC 95V 75W |
| VI-B6N-IV-F4 | CONVERTER MOD DC/DC 18.5V 150W |
| VI-B6N-IV-F2 | CONVERTER MOD DC/DC 18.5V 150W |
| ISL267440IUZ | IC INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R03ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R03IV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R03IV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3-Ch E3/DS3/STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R03IVTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R03IVTR-F | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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