XRT75R03D
81
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
Channel 1 Address Location = 0x0E
Channel 2 Address Location = 0x16
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/DS3_n
SR/DR_n
R/O
R/W
0
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
7 - 6
Unused
R/O
0
5
PRBS Enable
R/W
0
PRBS Generator and Receiver Enable - Channel_n:
This READ/WRITE bit-field is used to either enable or dis-
able the PRBS Generator and Receiver within a given
Channel of the XRT75R03D.
If the user enables the PRBS Generator and Receiver, then
the following will happen.
1. The PRBS Generator (which resides within the
Transmit Section of the Channel) will begin to
generate an unframed, 2^15-1 PRBS Pattern (for
DS3 and STS-1 applications) and an unframed,
2^23-1 PRBS Pattern (for E3 applications).
2. The PRBS Receiver (which resides within the
Receive Section of the Channel) will now be enabled
and will begin to search the incoming data for the
above-mentioned PRBS patterns.
0 - Disables both the PRBS Generator and PRBS Receiver
within the corresponding channel.
1 - Enables both the PRBS Generator and PRBS Receiver
within the corresponding channel.
NOTES:
1.
To check and monitor PRBS Bit Errors, Bit 0 (SR/
DR_n) within this register Must be set to "0". This
step will configure the RNEG_n/LCV_n output pin
to function as the PRBS Error Indicator. In this
case, external glue logic will be needed to monitor
and count the number of PRBS Bit Errors that are
detected by the PRBS Receiver.
2.
If the user enables the PRBS Generator and
PRBS Receiver, then the Channel will ignore the
data that is being accepted from the System-side
Equipment (via the TPDATA_n and TNDATA_n
input pins) and will overwrite this outbound data
with the PRBS Pattern.
3.
Use of the PRBS Generator and Receiver is only
available through the Host Mode.