參數(shù)資料
型號: XRT75R03DIVTR-F
廠商: Exar Corporation
文件頁數(shù): 93/135頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝: 750
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 帶卷 (TR)
XRT75R03D
56
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
REV. 1.0.4
0x11
Source Level
Interrupt Enable
Register - Ch 0
Reserved
Change
of
FL Alarm
Condi-
tion
Interrupt
Enable
Change of
RLOL
Condition
Interrupt
Enable
Change
of
RLOS
Defect
Condition
Interrupt
Enable
Change of
DMO
Condition
Interrupt
Enable
0x12
Source Level
Interrupt Status
Register - Ch 0
Reserved
Change
of
FL Alarm
Condi-
tion
Interrupt
Status
Change of
RLOL
Condition
Interrupt
Status
Change
of
RLOS
Condition
Interrupt
Status
Change of
DMO
Condition
Interrupt
Status
0x13
Alarm Status
Register - Ch 0
Reserved
Loss of
PRBS
Pattern
Sync
DLOS
Defect
Declared
ALOS
Defect
Declared
FL Alarm
Declared
RLOL
Condition
Declared
RLOS
Defect
Condition
DMO
Condition
Status
0x14
Transmit Control
Register - Ch 0
Reserved
Internal
Transmit
Drive
Monitor-
ing
Insert
PRBS
Error
Unused
TAOS
TxCLK
INV
TxLEV
0x15
Receive Control
Register - Ch 0
Reserved
DisableD-
LOS
Detector
DisableA-
LOS
Detector
RxCLK
INV
LOSMUTE
nable
Receive
Monitor
Mode
Enable
Receive
Equalizer
Enable
0x16
Channel Control
Register - Ch 0
Reserved
PRBS
Enable
RLB
LLB
E3 Mode
STS-1/
DS3
Mode
SR/DR
Mode
0x17
Jitter Attenuator
Control Register
- Ch 0
Reserved
SONET
APS
Recovery
Time Mode
Disable
JA
RESET
JA1
(JA Mode
Select Bit
1)
JA in
TxPath
JA0
(JA Mode
Select 0)
0x19 -
0x1F
Reserved
0x20
Block Level
Interrupt Enable
Register - Ch 32
0x21
Block Level
Interrupt Status
Register - Ch 33
TABLE 15: XRT75R03D REGISTER MAP - QUICK LOOK
ADDRES
S
LOCATIO
N
REGISTER NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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