XRT75R03D
4
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
REV. 1.0.4
PIN DESCRIPTIONS (BY FUNCTION)
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
38
1
125
TxON_0
TxON_1
TxON_2
I
Transmitter ON Input - Channel 0:
Transmitter ON Input - Channel 1:
Transmitter ON Input - Channel 2:
These input pins are used to either enable or disable the Transmit Output
Driver corresponding to Channel_n.
"Low" - Disables the Transmit Output Driver of the corresponding Channel.
In this setting, the corresponding TTIP_n and TRING_n output pins will be
tri-stated.
"High" - Enables the Transmit Output Driver of the corresponding Channel.
In this setting, the corresponding TTIP_n and TRING_n output pins will be
enabled.
NOTES:
1.
Even when the XRT75R03D is configured in HOST mode, these
pins will be active. To enable software control of the Transmit
Output Driver outputs, pull these pins "High".
2.
When Transmitters are turned off either in Host or Hardware
mode, the TTIP and TRing outputs are Tri-stated.
3.
These pins are internally pulled "High"
35
4
26
TxClk_0
TxClk_1
TxClk_2
I
Transmit Clock Input - Channel 0:
Transmit Clock Input f - Channel 1:
Transmit Clock Input - Channel 2:
These input pins have two functions:
They function as the timing source for the Transmit Section of the
corresponding channel within the XRT75R03D.
They also are used by the Transmit Section of the LIU IC to sample the
corresponding TPDATA_n and TNDATA_n input pin.
NOTE: The user is expected to supply a 44.736MHz ± 20ppm clock signal
(for DS3 applications), 34.368MHz ± 20 ppm clock signal (for E3
applications) or a 51.84MHz ± 4.6ppm clock signal (for STS-1,
Stratum 3E or better applications).