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參數(shù)資料
| 型號(hào)： | XRT75R03DIVTR-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 112/135頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 帶卷 (TR) |
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XRT75R03D
74
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
REV. 1.0.4
3
FL Alarm Declared
R/O
0
FL (FIFO Limit) Alarm Declared:
This READ-ONLY bit-field indicates whether or not the Jitter
Attenuator block (within Channel_n) is currently declaring
the FIFO Limit Alarm.
The Jitter Attenuator block will declare the FIFO Limit Alarm
anytime the Jitter Attenuator FIFO comes within two bit-
periods of either overflowing or under-running.
Conversely, the Jitter Attenuator block will clear the FIFO
Limit Alarm anytime the Jitter Attenuator FIFO is NO longer
within two bit-periods of either overflowing or under-running.
Typically, this Alarm will only be declared whenever there is
a very serious problem with timing or jitter in the system.
0 - Indicates that the Jitter Attenuator block (within
Channel_n) is NOT currently declaring the FIFO Limit Alarm
condition.
1 - Indicates that the Jitter Attenuator block (within
Channel_n) is currently declaring the FIFO Limit Alarm con-
dition.
NOTE:
This bit-field is only active if the Jitter Attenuator
(within Channel_n) has been enabled.
2
Receive LOL Condi-
tion Declared
R/O
0
Receive LOL (Loss of Lock) Condition Declared:
This READ-ONLY bit-field indicates whether or not the
Receive Section (within Channel_n) is currently declaring
the LOL (Loss of Lock) condition.
The Receive Section (of Channel_n) will declare the LOL
Condition, if any one of the following conditions are met.
If the frequency of the Recovered Clock signal differs
from that of the signal provided to the E3CLK input (for
E3
applications),
the
DS3CLK
input
(for
DS3
applications)
or
the
STS-1CLK
input
(for
STS-1
applications) by 0.5% (or 5000ppm) or more.
If the frequency of the Recovered Clock signal differs
from the line-rate clock signal (for Channel_n) that has
been generated by the SFM Clock Synthesizer PLL (for
SFM Mode Operation) by 0.5% (or 5000ppm) or more.
0 - Indicates that the Receive Section of Channel_n is NOT
currently declaring the LOL Condition.
1 - Indicates that the Receive Section of Channel_n is cur-
rently declaring the LOL Condition.
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
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| VI-B6N-IV-F2 | CONVERTER MOD DC/DC 18.5V 150W |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R03ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R03IV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R03IV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3-Ch E3/DS3/STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R03IVTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R03IVTR-F | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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