S
參數(shù)資料
型號: XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 2/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
7
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
TRANSMITTER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
TTIP
8
O
Transmitter Tip Output
Positive differential transmit output to the line.
TRING
10
O
Transmitter Ring Output
Negative differential transmit output to the line.
TPOS
TDATA
61
I
Transmitter Positive Data Input
In dual-rail mode, this signal is the positive-rail input data for the transmitter.
Transmitter Data Input
In single-rail mode, this pin is used as the NRZ input data for the transmitter.
NOTE: Internally pulled “Low” with a 50k
resistor.
TNEG
CODES
62
I
Transmitter Negative NRZ Data Input
In dual-rail mode, this signal is the negative-rail input data for the transmitter.
In single-rail mode, this pin can be left unconnected.
Coding Select
In Hardware Mode and with single-rail mode selected, connecting this pin
"Low" enables HDB3 in E1 or B8ZS in T1 encoding and decoding. Connect-
ing this pin "High" selects AMI data format.
NOTE: Internally pulled “Low” with a 50k
resistor.
TCLK
60
I
Transmitter Clock Input
E1 rate at 2.048MHz ± 50ppm
T1 rate at 1.544MHz ± 32ppm
During normal operation, both in Host Mode and Hardware Mode, TCLK is
used for sampling input data at TPOS/TDATA and TNEG/CODES while
MCLK is used as the timing reference for the transmit pulse shaping circuit.
TCLKE
57
I
Transmit Clock Edge
In Hardware Mode, with this pin set to a "High", transmit input data is sam-
pled at the rising edge of TCLK. With this pin tied "Low", input data are sam-
pled at the falling edge of TCLK.
NOTE: Internally pulled “Low” with a 50k
resistor.
TXON
58
I
Transmitter Turn On
In Hardware Mode, setting this pin "High" turns on the Transmit Section. In
this mode, when TXON = “0”, TTIP and TRING driver outputs will be tri-
stated.
In Host Mode, setting bit 5 (TXONCTL) to “1”, in Register 18 (12h), control of
the transmitter output is transferred to the hardware pin TXON.
NOTE: Internally pulled "Low" with a 50k
resistor.
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