XRT83SL30
51
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION
REGISTER ADDRESS
00100
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
GIE
Global Interrupt Enable:
Writing a "1" into this bit, globally
enables interrupt generation on the INT pin. Writing a "0" into this
bit, globally masks all interrupt requests.
R/W
0
D6
DMOIE
DMO Interrupt Enable:
Writing a "1" to this bit enables DMO
interrupt generation, writing a "0" masks it.
R/W
0
D5
FLSIE
FIFO Limit Status Interrupt Enable:
Writing a "1" to this bit
enables interrupt generation when the FIFO limit is within 3 bits,
writing a "0" to masks it.
R/W
0
D4
LCVIE
Line Code Violation Interrupt Enable:
Writing a "1" to this bit
enables Line Code Violation interrupt generation, writing a "0"
masks it.
R/W
0
D3
NLCDIE
Network Loop-Code Detection Interrupt Enable:
Writing a "1"
to this bit enables Network Loop-code detection interrupt genera-
tion, writing a "0" masks it.
R/W
0
D2
AISDIE
AIS Detection Interrupt Enable:
Writing a "1" to this bit enables
Alarm Indication Signal detection interrupt generation, writing a
"0" masks it.
R/W
0
D1
RLOSIE
Receive Loss of Signal Interrupt Enable:
Writing a "1" to this
bit enables Loss of Receive Signal interrupt generation, writing a
"0" masks it.
R/W
0
D0
QRPDIE
QRSS Pattern Detection Interrupt Enable:
Writing a "1" to this
bit enables QRSS pattern detection interrupt generation, writing
a "0" masks it.
R/W
0