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參數(shù)資料
型號(hào): XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 60/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
60
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 34: MICROPROCESSOR REGISTER #16 BIT DESCRIPTION
REGISTER ADDRESS
10000
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
D7
SR/DR
Single-rail/Dual-rail Select:
Writing a "1" to this bit configures
the XRT83SL30 to operate in the Single-rail mode.
Writing a "0" configures the XRT83SL30 to operate in Dual-rail
mode.
R/W
0
D6
ATAOS
Automatic Transmit All Ones Upon RLOS:
Writing a "1" to this
bit enables the automatic transmission of All Ones data to the
line.
Writing a "0" disables this feature.
R/W
0
D5
RCLKE
Receive Clock Edge:
Writing a "1" to this bit selects receive out-
put data to be updated on the negative edge of RCLK.
Writing a "0" selects data to be updated on the positive edge of
RCLK.
R/W
0
D4
TCLKE
Transmit Clock Edge:
Writing a "0" to this bit selects transmit
data at TPOS/TDATA and TNEG to be sampled on the falling
edge of TCLK.
Writing a "1" selects the rising edge of the TCLK for sampling.
R/W
0
D3
DATAP
DATA Polarity:
Writing a "0" to this bit selects transmit input and
receive output data of the XRT83SL30 to be active "High".
Writing a "1" selects an active "Low" state.
R/W
0
D2
Reserved
R/W
0
D1
Reserved
R/W
0
D0
SRESET
Software Reset
P Registers: Writing a "1" to this bit longer
than 10
s resets all internal state machines.
R/W
0
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