XRT83SL30
44
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 18: MICROPROCESSOR REGISTER #0 BIT DESCRIPTION
REGISTER ADDRESS
00000
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6
Reserved
R/W
0
D5
Reserved
R/W
0
D4
EQC4
Equalizer Control bit 4:
This bit together with EQC[3:0] are
used for controlling transmit pulse shaping and receive monitor-
ing.
See
Table 5 for description of Equalizer Control bits.
R/W
0
D3
EQC3
Equalizer Control bit 3:
See bit D4 description for function of
this bit
R/W
0
D2
EQC2
Equalizer Control bit 2:
See bit D4 description for function of
this bit
R/W
0
D1
EQC1
Equalizer Control bit 1:
See bit D4 description for function of
this bit
R/W
0
D0
EQC0
Equalizer Control bit 0:
See bit D4 description for function of
this bit
R/W
0