參數(shù)資料
型號(hào): XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 73/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
72
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
ORDERING INFORMATION
REVISION HISTORY
Rev. P1.0.0 Initial issue.
Rev. P1.0.1 Removed TERCNTL function (pin 46). Pins 61 and 62 are internally pulled Low. Set GIE bit to “0”
to globally disable interrupt generation.Bit 7 of control register 2 and bit 1 of control register 3 are Reserved.
Changed definition of Bits D6-D0 of tables 27 - 34. Removed references to long haul.
Rev. P1.0.3 Removed TERCNTL, TXTEST[[0:2], INSBPV from block diagram. Removed - Selectable receiver
sensitivity from 0 to 36dB cable loss, and - High Receiver Interface Immunity, from Features section. Edit
EQC[4:0] to be input only on block diagram. Corrected RXMUTE, TCLK, JABW, MCKLE1, CLKSEL [2:0],
RXTSEL, TERSEL[1:0], RXRES[1:0], EQC4, ATAOS, NLCD in the pin descriptions section. Replaced the
Functional Description section. Edits to Table 18: Microprocessor Register Bit Map, Table 21: Microprocessor
Register #2 Bit Description, Table 35: Microprocessor Register #16 Bit Description
Rev P1.0.4 Table 35: Microprocessor Register #17 Bit Description, edit E1 clock MCLKRATE= “0” and T1/J1
clock MCLKRATE=”1” .
Rev 1.0.0 Final Release
Rev. 1.0.1 Corrected package dimensions in ordering information, page 3.
TABLE 48.
PART #
PACKAGE
OPERATING TEMPERATURE RANGE
XRT83SL30IV
64 Pin TQFP
-40oC to +85oC
THERMAL INFORMATION
Theta - JA = 38° C/W
Theta JC = 7° C/W
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