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| 型號(hào)： | XRT83SL30IV-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 20/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 SGL 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類(lèi)型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 托盤(pán) |
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XRT83SL30
24
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and
TRING. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter has no output for more than 128 clock cycles, the corresponding DMO pin
goes “High” and remains “High” until a valid transmit pulse is detected. In Host mode, the failure of the transmit
channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any transition on the
DMO interface bit will generate an interrupt. The driver failure monitor is supported in both Hardware and Host
modes.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the EQC[4:0] pins determine the transmit pulse shape. In Host mode transmit pulse shape can be
controlled using the interface bits EQC[4:0]. The chip supports five fixed transmit pulse settings for T1 Short-
haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes.
The choice of the transmit pulse shape under the control of the interface bits are summarized in Table 5.
NOTE:
EQC[4:0] determine the T1/E1 operating mode of the XRT83SL30. When EQC4 = “1” and EQC3 = “1”, the
XRT83SL30 is in the E1 mode, otherwise it is in the T1/J1 mode.
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4
EQC3
EQC2
EQC1
EQC0
T1/E1 MODE & RECEIVE
SENSITIVITY
TRANSMIT LBO
CABLE
CODING
0
1
0
T1 Short Haul/15dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1
0
1
T1 Short Haul/15dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
0
1
0
1
0
T1 Short Haul/15dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
0
1
0
1
T1 Short Haul/15dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
0
1
0
T1 Short Haul/15dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
0
1
0
1
T1 Short Haul/15dB
Arbitrary Pulse
100
/ TP
B8ZS
0
1
0
T1 Gain Mode/29dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1
T1 Gain Mode/29dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
1
0
T1 Gain Mode/29dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
1
0
1
T1 Gain Mode/29dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
1
0
1
0
T1 Gain Mode/29dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
1
0
1
T1 Gain Mode/29dB
Arbitrary Pulse
100
/ TP
B8ZS
1
0
E1 Short Haul
ITU G.703
75
Coax
HDB3
1
0
1
E1 Short Haul
ITU G.703
120
TP
HDB3
1
0
E1 Gain Mode
ITU G.703
75
Coax
HDB3
1
E1 Gain Mode
ITU G.703
120
TP
HDB3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SL30IVTR-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL314 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL314_05 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL314ES | 功能描述:LIN 收發(fā)器 14 CHT1/E1 LIUSH RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT83SL314IB | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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