參數(shù)資料
型號: XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 36/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標準包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
38
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REMOTE LOOP-BACK (RLOOP)
With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in Figure 19.
In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in Figure 20.
FIGURE 19. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH
FIGURE 20. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
JA
Tx
Decoder
Timing
Control
Rx
Clock &
Data
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
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