參數(shù)資料
型號: XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 75/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標準包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
5
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
PIN DESCRIPTIONS BY FUNCTION
SERIAL INTERFACE
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
HW/HOST
20
I
Mode Control Input
This pin is used for selecting Hardware or Host Mode to control the device.
Leave this pin unconnected or tie “High” to select Hardware Mode.
For Host Mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50k
resistor.
SDI
EQC4
21
I
Serial Data Input
In Host Mode, this pin is the data input for the Serial Interface.
Equalizer Control Input 4
SDO
EQC3
22
O
I
Serial Data Output
In Host Mode, this pin is the output “Read” data for the serial interface.
Equalizer Control Input 3
SCLK
EQC2
23
I
Serial Interface Clock Input
In Host Mode, this clock signal is used to control data “Read” or “Write” oper-
ation for the Serial Interface. Maximum clock frequency is 20MHz.
Equalizer Control Input 2
CS
EQC1
24
I
Chip Select Input
In Host Mode, tie this pin “Low” to enable communication with the device via
the Serial Interface.
Equalizer Control Input 1
INT
EQC0
25
O
I
Interrupt Output (active "Low")
In Host Mode, this pin goes “Low” to indicate an alarm condition has
occurred within the device. Interrupt generation can be globally disabled by
setting the GIE bit to “0” in the command control register.
Equalizer Control Input 0
NOTE: This pin is an open drain output and requires an external 10k
pull-
up resistor.
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