參數(shù)資料
型號: XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 44/76頁
文件大小: 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
46
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
D3
JASEL1
Jitter Attenuator select bit 1:
The JASEL1 and JASEL0 bits are
used to disable or place the jitter attenuator in the transmit or
receive path.
R/W
0
D2
JASEL0
Jitter Attenuator select bit 0:
See description of bit D3 for the
function of this bit.
R/W
0
D1
JABW
Jitter Attenuator Bandwidth Select:
In E1 mode, set this bit to "1" to select a 1.5Hz Bandwidth for the
Jitter Attenuator In E1 mode. The FIFO length will be automati-
cally set to 64 bits.
Set this bit to "0" to select 10Hz Bandwidth for the Jitter Attenua-
tor in E1 mode.
In T1 mode the Jitter Attenuator Bandwidth is permanently set to
3Hz, and the state of this bit has no effect on the Bandwidth.
R/W
0
D0
FIFOS
FIFO Size Select:
See table of bit D1 above for the function of
this bit.
R/W
0
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION
JASEL1
bit D3
JASEL0
bit D2
0
1
0
1
JA Path
JA Disabled
JA in Transmit Path
JA in Receive Path
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
1
0
1
JABW
bit D1
T1
E1
Mode
32
64
32
64
32
64
FIFO
Size
3
10
1.5
JA B-W
Hz
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