參數(shù)資料
型號： XRT91L80IB-F
廠商： Exar Corporation
文件頁數(shù)： 20/46頁
文件大小： 0K
描述： IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告： XRT91L80IB Obsolescence 6/Sept/2010
標準包裝： 126
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA
供應商設備封裝： 196-STBGA（12x12）
包裝： 托盤
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
19
3.2
Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 10 and Table 6.
FIGURE 10. TRANSMIT PARALLEL INPUT TIMING
TABLE 6: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION
TABLE 7: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION
3.3
Transmit FIFO
The parallel interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the
input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an
arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be initialized
when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the FIFO_RST is
de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is centered, the
delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of the low-speed
clock. Should the delay exceed this amount, the read and write pointers will point to the same Nibble in the
FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the FIFO control
logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO RESET
signal. The device under the control of the FIFO_AUTORST pin can automatically recover from an overflow
condition. When the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tTXPCLKI
Transmit parallel clock input period (622.08 MHz non-FEC rate)
1608
ps
tTXPCLKI
Transmit parallel clock input period (666.51 MHz FEC rate)
1500
ps
tTXDI_SU
TXPCLKIP/N "High" to data setup time
300
ps
tTXDI_HD
TXPCLKIP/N "High" to data hold time
300
ps
TXDUTY
TXPCLKIP/N Duty Cycle
40
60
%
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tTXPCLKO
Transmit parallel clock output period (622.08 MHz non-FEC rate)
1608
ps
tTXPCLKO
Transmit parallel clock output period (666.51 MHz FEC rate)
1500
ps
TXDUTY
TXPCLKOP/N Duty Cycle
45
58
%
TXPCLKIP/N
TXDI[15:0]P/N
tTXDI_SU
tTXDI_HD
tTXPCLKI
tTXPCLKO
TXPCLKOP/N
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