- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2121 > XRT91L80IB-F (Exar Corporation)IC TXRX SONET/SDH 4BIT 196STBGA PDF資料下載
參數(shù)資料
| 型號： | XRT91L80IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 32/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 產(chǎn)品變化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 標準包裝： | 126 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA |
| 供應商設備封裝： | 196-STBGA（12x12） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
35
TABLE 15: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
TABLE 16: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CONFIGURATION 1 CONTROL REGISTER (0X04H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
POLARITY
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W
0
D5
LOOPTM_JA
Loop Timing With Jitter Attenuation
The LOOPTM_JA bit must be set to "1" in order to select the recov-
ered receive clock as the reference source for the de-jitter PLL.
"0" = Disabled
"1" = Loop timing with de-jitter PLL Activated
R/W
0
D4
LOOPTM_
NOJA
Loop Timing With No Jitter Attenuation
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/32nd
of the high-speed recovered receive clock coming from the CDR.
"0" = Disabled
"1" = Loop timing Activated
R/W
0
D3
LOSDMUTE
Parallel Receive Data Output Mute Upon LOSD
If this bit is set to "1", the receive data output will automatically be
forced to a logic state of "0" when an LOSD condition occurs.
"0" = Disabled
"1" = Mute RXDO[3:0]P/N Data Upon LOSD Condition
R/W
0
D2
DISRD
Parallel Receive Data Output Disable
This bit is used to disable the RXDO[3:0]P/N parallel receive data
output bus asynchronously.
"0" = Normal Mode
"1" = Forces RXDO[3:0]P/N to a logic state "0"
R/W
0
D1
Reserved
Reserved - Set to 0
R/W
0
D0
VCXOLKEN
De-Jitter PLL Lock Detect Enable
This bit enables the VCXO_INP/N lock detect circuit to be active.
"0" = VCXO Lock Detect Disabled
"1" = VCXO Lock Detect Enabled
R/W
0
DIAGNOSTIC CONTROL REGISTER (0X05H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
Reserved
This Register Bit is Not Used
X
相關PDF資料 |
PDF描述 |
|---|---|
| ZSD100N8TA | IC DRIVER SIREN 8-SOIC |
| ZXCD1210JB16TA | IC AMP AUDIO CLASS D 16QFN |
| ZXFV203N14TC | IC AMP VIDEO CFA 3CHAN 14SOIC |
| 020189 | FAN 115VAC 254X89MM CLE2T2 |
| 020191 | FAN 230VAC 254X89MM CLE3T2 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L81 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。