參數(shù)資料
型號(hào)： XRT91L80IB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 22/46頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告： XRT91L80IB Obsolescence 6/Sept/2010
標(biāo)準(zhǔn)包裝： 126
類(lèi)型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 196-LFBGA
供應(yīng)商設(shè)備封裝： 196-STBGA（12x12）
包裝： 托盤(pán)
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
21
3.6
Clock Multiplier Unit (CMU) and Re-Timer
The high-speed serial clock synthesized by the CMU is divided by 4, and is presented to the upstream device
as TXPCLKOP/N clock . The upstream device should use TXPCLKOP/N as its timing source. The upstream
device then generates the TXPCLKIP/N clock that is phase aligned with the transmit data and provides it to the
parallel interface of the transmitter. The data must meet setup and hold times with respect to TXPCLKIP/N.
The XRT91L80 will latch TXDI[3:0]P/N on the rising edge of TXPCLKIP/N. The clock synthesizer uses a PLL
to lock to the differential input reference clock REFCLKP/N. It will then use this reference clock to generate the
2.488/2.666 GHz STS-48/STM-16 serial clock and in addition feed this high-speed synthesized clock to the
PISO. The Retimer will then align the transmit serial data from the PISO with this 2.488/2.666 GHz synthesized
clock to generate the output TXOP/N. REFCLKP/N input can accept a clock from a differential LVPECL crystal
oscillator that has a frequency accuracy better than 20ppm in order for the high-speed transmit serial clock
frequency to have the accuracy required for SONET systems. Table 8 specifies the Clock Multiplier Unit
performance characteristics.
The CMU can also be driven by an optional external VCXO for loop timed or local reference de-jitter
applications. VCXO_INP/N can be connected to the output of a VCXO that can be configured to clean up the
recovered received clock coming from CP_OUT in loop timing mode before being applied to the input of the
transmit CMU as a reference clock. In addition, the internal phase/frequency detector and charge pump,
combined with an external VCXO can alternately be used as a jitter attenuator to de-jitter a noisy system
reference clock such as REFCLKP/N prior to it being used to time the CMU. The following Section 3.7, “Loop
Timing and Clock Control,” on page 21 illustrate the use of this method.
TABLE 8: CLOCK MULTIPLIER UNIT PERFORMANCE
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1Required to meet SONET output frequency stability requirements.
3.7
Loop Timing and Clock Control
Two types of loop timing are possible in the XRT91L80.
In the regular loop timing mode (without an external VCXO), loop timing is controlled by the LOOPTM_NOJA
pin. This mode is selected by asserting the LOOPTM_NOJA signal to a "High" level. When the loop timing
mode is activated, the external local reference clock to the input of the CMU is replaced with the 1/16th or the
1/32nd of the high-speed recovered receive clock coming from the CDR. Under this condition both the transmit
and receive sections are synchronized to the recovered receive clock. The normal looptime mode directly locks
the CMU to the recovered receive clock with no external de-jittering.
Loop timing performance can be further improved using an external VCXO-based PLL to clean up the jitter of
the recovered receive clock. In this case the VCXO_SEL pin should be set "High." By doing so, the CMU
receives its reference clock signal from an external VCXO connected to the VCXO_INP/N inputs. The
LOOPTM_JA pin must also be set "High" in order to select the recovered receive clock as the reference source
for the de-jitter PLL. In this state, the VCXO will be phase locked to the recovered receive clock through a
narrowband loop filter. The use of the on-chip phase/frequency detector with charge pump and an external
VCXO to remove the transmit jitter due to jitter in the recovered clock is shown in Figure 13.
NAME
PARAMETER
MIN
TYP
MAX
UNITS
REFDUTY
Reference clock duty cycle
45
55
%
REFTOL
Reference clock frequency tolerance1
-20
+20
ppm
REFSTS48
Reference clock jitter limits from 12 KHz to 20 MHz
-61
dBC
OCLKJIT
Clock output jitter generation with 77.76 MHz reference clock
3.1
4.0
mUIrms
OCLKJIT
Clock output jitter generation with 155.52 MHz reference clock
2.5
3.0
mUIrms
OCLKFREQ
Frequency output
2.488
2.667
GHz
OCLKDUTY
Clock output duty cycle
45
58
%
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