NAME
參數(shù)資料
型號： XRT91L80IB-F
廠商： Exar Corporation
文件頁數(shù)： 3/46頁
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告： XRT91L80IB Obsolescence 6/Sept/2010
標準包裝： 126
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA
供應商設備封裝： 196-STBGA（12x12）
包裝： 托盤
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
9
RECEIVER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
RXDO0P
RXDO0N
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
LVDS
O
E13
F13
C14
D14
C13
D13
A14
B14
Receive Parallel Data Output
622Mbps 4-bit parallel receive data output is updated simulta-
neously on the rising edge of the RXPCLKOP/N output. The 4-
bit parallel interface is de-multiplexed from the receive serial
data input MSB first (RXDO3P/N).
NOTE: The XRT91L80 can output 666.51 Mbps 4-bit parallel
receive data output for Forward Error Correction (FEC)
Applications.
RXPCLKOP
RXPCLKON
LVDS
O
E14
F14
Receive Parallel Clock Output
622.08 MHz parallel clock output used to update the 4-bit paral-
lel receive data output RXDO[3:0]P/N at the rising edge of this
clock..
NOTE: The XRT91L80 can output a 666.51 MHz receive clock
output for Forward Error Correction (FEC).
DISRD
LVTTL
LVCMOS
I
C12
Parallel Receive Data Output Disable
This pin is used to disable the RXDO[3:0]P/N parallel receive
data output bus asynchronously.
"Low" = Normal Mode
"High" = Forces RXDO[3:0]P/N to a logic state "0"
This pin is provided with an internal pull-down.
RXIP
RXIN
CMLDIFF
I
C1
D1
Receive Serial Data Input
The receive serial data stream of 2.488 Gbps is applied to
these input pins. In Forward Error Correction, the receive
serial data stream is 2.666 Gbps.
XRES1P
XRES1N
-
I
G1
F1
External LVDS Biasing Resistors
A 402
resistor with +/-1% tolerance should be placed across
these 2 pins for proper biasing.
RXCLKO16P
RXCLKO16N
LVDS
O
A6
A7
Auxiliary Clock Output (155.52/166.63 MHz)
155.52/166.63 MHz auxiliary clock derived from divide-by-16
CDR recovered clock.
LOCKDET_CDR
LVCMOS
O
C7
CDR Lock Detect
This pin is used to monitor the lock condition of the clock and
data recovery unit.
"Low" = CDR Out of Lock
"High" = CDR Locked
SDEXT
LVTTL,
LVCMOS
I
B5
Signal Detect Input from Optical Module
Hardware Mode When inactive, it will immediately declare a
Loss of Signal Detect (LOSD) condition and assert LOSDET
output pin and control the activity of the RXDO[3:0]P/N parallel
data output based on LOSDMUTE pin setting.
Host Mode In addition to asserting LOSDET output pin, it will
update the LOSD condition on the registers and control the
activity of the RXDO[3:0]P/N parallel data output based on
LOSDMUTE register bit setting.
"Active" = Normal Operation
"Inactive" = LOSD Condition (SDEXT detects signal absence)
This pin is provided with an internal pull-down.
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