參數(shù)資料
型號(hào)： XRT91L80IB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 31/46頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告： XRT91L80IB Obsolescence 6/Sept/2010
標(biāo)準(zhǔn)包裝： 126
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA
供應(yīng)商設(shè)備封裝： 196-STBGA（12x12）
包裝： 托盤
XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
34
D4
LOOPBW
CMU Loop Band Width Select
This bit is used to select the bandwidth of the clock multiplier unit
of the transmit path to a narrow or wide band. Use Wide Band for
clean reference signals and Narrow Band for noisy references.
"0" = Wide Band (4x)
"1" = Narrow Band (1x)
R/W
0
D3
VCXO_SEL
VCXO De-Jitter Select
This bit selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N as a reference clock.
"0" = Normal REFCLKP/N Mode
"1" = De-Jitter VCXO Mode
R/W
0
D2
TXCLKO16DIS
Auxiliary Clock Disable
This bit is used to control the activity of the auxiliary clock.
"0" = TXCLKO16P/N Enabled
"1" = TXCLKO16P/N Disabled
R/W
0
D1
FIFO_
AUTORST
Automatic FIFO Overflow Reset
If this bit is set to "1", the STS-48/STM-16 transceiver will automat-
ically flush the FIFO upon an overflow condition. Upon power-up,
the FIFO should be manually reset by setting FIFO_RST to "1" for
a minimum of 2 TXPCLKOP/N cycles.
"0" = Manual FIFO reset required for Overflow Conditions
"1" = Automatically resets FIFO upon Overflow Detection
R/W
0
D0
FIFO_RST
Manual FIFO Reset
FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N
cycles after powering up and during manual FIFO reset. After the
FIFO_RST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N
cycles for the FIFO to flush out. Upon an interrupt indication that
the FIFO has an overflow condition, this bit is used to reset or flush
out the FIFO.
"0" = Normal Operation
"1" = Manual FIFO Reset
NOTE: To automatically reset the FIFO, see the FIFO_AUTORST
bit.
R/W
0
TABLE 14: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
CONFIGURATION 0 CONTROL REGISTER (0X03H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
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