參數(shù)資料
型號(hào): XRT91L80IB-F
廠商: Exar Corporation
文件頁數(shù): 26/46頁
文件大小: 0K
描述: IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告: XRT91L80IB Obsolescence 6/Sept/2010
標(biāo)準(zhǔn)包裝: 126
類型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 196-LFBGA
供應(yīng)商設(shè)備封裝: 196-STBGA(12x12)
包裝: 托盤
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
29
5.0
SERIAL MICROPROCESSOR INTERFACE BLOCK
The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the
transceiver.
Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the
registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default configuration by
pulling reset "Low" for more than 10ms. A simplified block diagram of the Serial Microprocessor is shown in
Figure 24.
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE
5.1
SERIAL TIMING INFORMATION
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16
bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 25.
FIGURE 25. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE
NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active
"Low") must be de-asserted at the end of every single write or single read operation.
Serial
Microprocessor
Interface
CS
SDI
SCLK
SDO
RESET
INT
HW/Host
CS
SDI
SCLK
SDO
1
2
10
9
8
7
6
5
4
3
11
16
15
13
14
12
R/W
A0
A1
A2
A3
A4
A5
X
D0
D1
D7
D6
D5
D4
D3
D2
D0
D1
D7
D6
D5
D4
D3
D2
High-Z
25nS
50nS
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