參數(shù)資料
型號(hào)： XRT91L80IB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 46/46頁(yè)
文件大小： 0K
描述： IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告： XRT91L80IB Obsolescence 6/Sept/2010
標(biāo)準(zhǔn)包裝： 126
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA
供應(yīng)商設(shè)備封裝： 196-STBGA（12x12）
包裝： 托盤
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
7
ALTFREQSEL
LVTTL,
LVCMOS
I
P1
Reference Clock Frequency Select
This pin is used to select the frequency of the REFCLKP/N
clock input to the CMU.
"Low" = 77.76 MHz (83.31 MHz for FEC)
"High" = 155.52 MHz (166.63 MHz for FEC)
This pin is provided with an internal pull-up.
VCXO_SEL
LVTTL,
LVCMOS
I
M6
De-Jitter VCXO Select Option
This pin selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N pin as a reference clock to the CMU.
"Low" = Normal REFCLKP/N reference clock
"High" = De-Jitter VCXO_INP/N reference clock
This pin is provided with an internal pull-down.
VCXO_LOCK
LVCMOS
O
N8
De-Jitter PLL Lock Detect
If the de-jitter PLL lock detect is enabled with pin P3 and the de-
jitter VCXO mode is selected by pin M6, this pin will assert
"High" when the PLL is locked.
"Low" = VCXO Out of Lock
"High" = VCXO Locked
VCXO_LOCKEN
LVTTL,
LVCMOS
I
P3
De-Jitter PLL Lock Detect Enable
This pin enables the VCXO_INP/N lock detect circuit and
VCXO_LOCK pin N8 to be active.
"Low" = VCXO Lock Detect Disabled
"High" = VCXO Lock Detect Enabled
This pin is provided with an internal pull-down.
CPOUT
-
O
P8
Charge Pump Output (for external VCXO)
The nominal output of the charge pump current is 250
A
LOOPBW
LVTTL,
LVCMOS
I
M7
CMU Loop Bandwidth Select
This pin is used to select the bandwidth of the clock multiplier
unit of the transmit path to a narrow or wide band. Use Wide
Band for clean reference signals and Narrow Band for noisy ref-
erences.
"Low" = Wide Band (4x)
"High" = Narrow Band (1x)
This pin is provided with an internal pull-down.
TXPCLKOP
TXPCLKON
LVDS
O
P10
P11
Transmit Parallel Clock Output
This 622.08 MHz clock can be used for the downstream device
to generate the TXDI[3:0]P/N data and TXPCLKIP/N clock
input. This enables the downstream device and the STS-48/
STM-16 transceiver to be in synchronization.
NOTE: The XRT91L80 can output a 666.51 MHz transmit clock
output for Forward Error Correction (FEC).
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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