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參數(shù)資料
| 型號： | XRT91L80IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 44/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 產(chǎn)品變化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 196-STBGA（12x12） |
| 包裝： | 托盤 |
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XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
5
HARDWARE COMMON CONTROL
NAME
LEVEL
TYPE
PIN
DESCRIPTION
RLOOPS
LVTTL,
LVCMOS
I
C10
Serial Remote Loopback
The serial remote loopback mode interconnects the receive
serial data input to the transmit serial data output. If serial
remote loopback is enabled, the 4-bit parallel transmit data
input is ignored while the 4-bit parallel receive data output is
maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature.
This pin is provided with an internal pull-down.
RLOOPP
LVTTL,
LVCMOS
I
A11
Parallel Remote Loopback
The parallel remote loopback mode allows the serial data input
stream to pass through the clock and data recovery circuit and
looped-back at the parallel interface to the serial output port.
The 4-bit parallel transmit data input is ignored while the 4-bit
parallel receive data output is maintained.
"Low" = Disabled
"High" = Parallel Remote Loopback Mode Enabled
NOTE:
DLOOP and RLOOPS should be disabled when
RLOOPP is enabled. The internal FIFO should also be
flushed using FIFO_RST pin or register bit when
parallel remote loopback is enabled/disabled.
This pin is provided with an internal pull-down.
DLOOP
LVTTL,
LVCMOS
I
B6
Digital Local Loopback
The digital local loopback mode interconnects the 4-bit parallel
transmit data and parallel transmit clock input to the 4-bit paral-
lel receive data and parallel receive clock output respectively
while maintaining the transmit serial data output. If digital local
loopback is enabled, the receive serial data input is ignored.
"Low" = Disabled
"High" = Digital Local Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature.
This pin is provided with an internal pull-down.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L81 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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