10
Simple System Interface for UltraNAND Flash
/** Declarations and Intermediate Variable Definitions **/
PORT0 = CE & !A3 & !A2 & !A1 & !A0 /* Data read/write port */
# INIT & !A1 & !A0;
PORT1 = CE & !A3 & !A2 & !A1 & A0 /* CLE write port */
# INIT & !A1 & A0;
PORT2 = CE & !A3 & !A2 & A1 & !A0 /* Used to set ALE */
# INIT & A1 & !A0;
PORT3 = CE & !A3 & !A2 & A1 & A0 /* Used to clear ALE */
# INIT & A1 & A0;
PORT4 = CE & !A3 & A2 & !A1 & !A0; /* Used to set SE# */
PORT5 = CE & !A3 & A2 & !A1 & A0; /* Used to clear SE# */
PORT6 = CE & !A3 & A2 & A1 & !A0; /* Used to set WP# */
PORT7 = CE & !A3 & A2 & A1 & A0; /* Used to clear WP# */
PORT8 = CE & A3 & !A2 & !A1 & !A0; /* Used to set OUTCE# */
PORT9 = CE & A3 & !A2 & !A1 & A0; /* Used to clear OUTCE# */
PORTA = CE & A3 & !A2 & A1 & !A0; /* No Function */
PORTB = CE & A3 & !A2 & A1 & A0; /* No Function */
PORTC = CE & A3 & A2 & !A1 & !A0; /* No Function */
PORTD = CE & A3 & A2 & !A1 & A0; /* No Function */
PORTE = CE & A3 & A2 & A1 & !A0; /* No Function */
PORTF = CE & A3 & A2 & A1 & A0; /* To read RY/BY# state */
/** Logic Equations **/
READY.OE = PORTF & READ; /* READY is only driven during a PORTF read */
READY = RY_BY; /* READY shows the state of RY/BY# */
CLE = PORT1; /* Assert CLE on all PORT1 accesses */
ALE = !RESET & ( WRITE & PORT2 /* Latch ALE on write to PORT2 */
# ALE & !( WRITE & PORT3 ) /* and clear on write to PORT3 */
# ALE & PORT2 ); /* Transparent latch cover term */
SE = RESET /* Latch SE# asserted on RESET */
# WRITE & PORT4 /* Latch SE# on write to PORT4 */
# SE & !( WRITE & PORT5 ) /* and clear on write to PORT5 */
# SE & PORT4; /* Transparent latch cover term */
WP = RESET /* Latch WP# asserted on RESET */
# WRITE & PORT6 /* Latch WP# on write to PORT6 */
# WP & !( WRITE & PORT7 ) /* and clear on write to PORT7 */
# WP & PORT6; /* Transparent latch cover term */
OUTCE = !RESET & ( INIT /* Latch OUTCE# asserted on INIT */
# WRITE & PORT8 /* Latch OUTCE# on write to PORT2 and */
# OUTCE & !( WRITE & PORT9 ) /* clear on write to PORT3 */
# OUTCE & PORT8 ); /* Transparent latch cover term */
WE = WRITE & ( PORT0 /* Drive WE# to UltraNAND for PORT0 or PORT1 */
# PORT1 );
RE = READ & PORT0; /* Drive RE# to UltraNAND for PORT0 only */