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參數(shù)資料
| 型號： | 22363A |
| 英文描述： | Simple System Interface for UltraNAND Flash |
| 中文描述： | 簡單的系統(tǒng)接口UltraNAND閃光 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 725K |
| 代理商： | 22363A |
6
Simple System Interface for UltraNAND Flash
Other Signals (Generated by the System Logic)
■
A[0..3] are the four least significant address bits,
generated by the system, which are used to select
one of sixteen ports in the Interface PLD.
■
CE# is generated by the system logic and deter-
mines the address that the Interface PLD and Ul-
traNAND devices will occupy. The system may
assign the CE# decode address to be any consec-
utive sixteen port address in either the I/O or mem-
ory address space.
■
INIT is generated by an optional “Boot Loader” PLD
which is only required if the system needs to read
from the device immediately after power-up. The
boot loader issues a Gapless Read (02h) command
sequence to the UltraNAND device, or devices, to
pre-load the data registers of each device with the
first page of information.
■
READ# is the system generated read strobe that is
used to read from the Interface PLD or UltraNAND
devices. In addition to the CE# input, the READ#
signal determines if the Interface PLD and Ul-
traNAND read operations are I/O or memory
mapped.
■
RESET is generated by the system and is used to
initialize the Interface PLD. The RESET signal
should be asserted (high) whenever the system
power is ramping up or down. This allows the Inter-
face PLD to assert WP# to protect the UltraNAND
devices from data corruption during power transi-
tions.
■
RY/BY# is generated by the UltraNAND device to
indicate when the device is busy with an internal op-
eration. The system may use the RY/BY# hardware
signal, or poll the RY/BY# status bit in the status
register, to determine when an operation is in pro-
cess, or has completed.
■
WRITE# is the system generated write strobe used
to write to the Interface PLD or UltraNAND devices.
In addition to the CE# input, the WRITE# signal is
used to determine if the Interface PLD and Ul-
traNAND write operations are I/O or memory
mapped.
Design Notes
With the simple interface described in this application
note, the system has full control of up to three Ul-
traNAND devices. There are a number of basic modi-
fications that can be made to the design to allow
different system configurations to be supported.
Modifications to WP# Circuit
In many applications, the WP# input to UltraNAND is
not dynamically controlled by the system. Instead it is
controlled by a jumper, or switch, that allows the circuit
to be hardware protected against program or erase cy-
cles. For this modification to the simple system inter-
face, the PLD output for WP# would be replaced with a
jumper or switch. Again, some form of RESET signal
must be used to force WP# active (low) during power
transitions.
Removing WP# from the Interface PLD would free up
an output pin and would allow a fourth chip enable out-
put to be supported. This would allow the Interface
PLD to support up to four banks of UltraNAND instead
of only three banks.
Supporting Multiple UltraNAND Banks
The simple system interface provided supports up to
three UltraNAND banks with all of the signals gener-
ated by the Interface PLD, except the output chip en-
ables common to all devices. The diagram in Figure 3
shows how two banks, with two UltraNAND devices in
each bank, can be supported. In this application, the
WP# signal is common to all of the Flash devices so
that the entire array is either protected or unprotected
as a block. If preferred, the logic to generate WP#
could be modified to provide a separate WP# for each
device.
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