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| 型號(hào)： | 22363A |
| 英文描述： | Simple System Interface for UltraNAND Flash |
| 中文描述： | 簡(jiǎn)單的系統(tǒng)接口UltraNAND閃光 |
| 文件頁(yè)數(shù)： | 6/21頁(yè) |
| 文件大?。?/td> | 725K |
| 代理商： | 22363A |
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Simple System Interface for UltraNAND Flash
5
Output Signal Generation
The simple system Interface PLDs use combinatorial
logic and transparent latches to generate all of the sig-
nals required by UltraNAND. CLE, RE#, and WE# are
generated dynamically and are not latched. ALE,
OUTCE[0..2]#, SE#, and WP# are latched in the de-
sign so that the system has the ability to set or clear
these signals as needed.
■
CLE is a dynamic signal which is generated when-
ever the system performs an access to port 01h.
This causes CLE to go active during both reads and
writes to port 01h. When the system writes a com-
mand out to port 01h, the command on the Ul-
traNAND I/O bus will be written with CLE active,
allowing the command to be accepted by the de-
vice. Prior to a command being written to the device
ALE must be cleared (ALE = low) and the chip en-
able for the appropriate UltraNAND device must be
latched low.
■
ALE is a latched signal which may be set or cleared
under software control and determines whether ad-
dresses, commands, or data are written to Ul-
traNAND. ALE must be cleared when a command
or data is to be written. Once ALE is set, the ad-
dress may be written to port 00h to load the address
into UltraNAND. ALE must be set prior to the first
address cycle written and must be cleared following
the last address write cycle. In the Interface PLD,
the latch is set and cleared by writing to ports 02h
and 03h respectively. Only a write to the port is re-
quired and the data written is irrelevant. In the
PLDs, ALE is latched low (cleared) following power-
up.
■
OUTCE[0..2]# are latched signals which may be set
or cleared under software control and determine
whether an UltraNAND device is enabled or dis-
abled. The appropriate chip enable output must be
set when a command, address, or data is to be writ-
ten to any UltraNAND device. The appropriate chip
enable output must also be set for any read opera-
tion, and must be held asserted during all read la-
tency periods to avoid aborting the requested read
operation. In the Interface PLD, the latch for
OUTCE0# is set and cleared by writing to ports 08h
and 09h, the latch for OUTCE1# is set and cleared
by writing to ports 0Ah and 0Bh, and OUTCE2# is
set and cleared by writing to ports 0Ch and 0Dh re-
spectively. Only a write to the port is required and
the data written is irrelevant. In the PLDs, all
OUTCE[0..2]# outputs are high (cleared) following
power-up.
■
RE# is a dynamic signal which is generated when-
ever the system performs a read from the Interface
PLD port 00h or 0Fh. This allows the system to
read Data, ID, or Status information from Ul-
traNAND through port 00h, or to read the state of
the RY/BY# pin(s) through the Interface PLD port
0Fh.
■
READY is a dynamic, tri-state output from the Inter-
face PLD that allows the system to read the state of
the UltraNAND RY/BY# pin(s). The Interface PLD
will drive the state of the RY/BY# pin(s) to the
READY pin when a read from Interface PLD port
0Fh is performed.
■
SE# is a latched signal which may be set or cleared
under software control and determines if the spare
area of each page (bytes 512 – 527) can be read or
written. Once SE# is set, the system may read or
write to the spare area through port 00h. SE# must
be set prior to the Read Spare Area command (50h)
being written to the device. If the spare area is to be
read or written along with the normal Flash page in-
formation (bytes 0 – 511) then SE# must be set at
least two cycles before the first spare area address
(512) is accessed. In the PLD, SE# is set and
cleared by writing to ports 04h and 05h respectively.
Only a write to the port is required and the data writ-
ten is irrelevant. SE# is latched low (set) following
power-up.
■
WE# is a dynamic signal which is generated when-
ever the system performs a write to the Interface
PLD port 00h or 01h. This allows the system to
write Address or Data information to UltraNAND
through port 00h, or to write commands to Ul-
traNAND through the Interface PLD port 01h.
■
WP# is a latched signal which is set or cleared
under software control, and determines whether or
not program or erase operations are allowed in Ul-
traNAND. Once WP# is set (low) the system is un-
able to program or erase any location in the device,
and only read cycles are allowed. In the PLD, the
WP# latch is set or cleared by a write to port 06h or
07h respectively. Only a write to the port is required
and the data written is irrelevant.
WP# is latched low (set) following power-up. A
RESET signal, which remains low until power is
valid, should be used to guarantee that WP# is as-
serted during power transitions. This is a require-
ment of UltraNAND and NAND technology devices,
and is used to guarantee that there is no data cor-
ruption in the device during power transitions.
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