參數(shù)資料
型號(hào): 22363A
英文描述: Simple System Interface for UltraNAND Flash
中文描述: 簡(jiǎn)單的系統(tǒng)接口UltraNAND閃光
文件頁數(shù): 15/21頁
文件大?。?/td> 725K
代理商: 22363A
14
Simple System Interface for UltraNAND Flash
PLD Source Code for UNISA22
This example includes the PLD source code and the simulation file used to verify a slightly modified PLD design.
The PLD circuit included below supports up to three UltraNAND banks. The AMD AmPALLV22V10-10PC used in
the example powers up in a known state which covers initial power-up conditions. The RESET input is used to ini-
tialize the transparent latches in the PLD. Figure 5 is a diagram showing the pin-out of the AmPALLV22V10-10PC
used in this design example.
Name UNISA22;
Partno PLD001;
Date 03/23/99;
Revision 0;
Designer Ralph Gibson;
Company Advanced Micro Devices;
Assembly UltraNAND(TM) ISA Development Board Interface Solution;
Location U1;
Device P22V10;
Format J;
/****************************************************************************\
** This is a simple interface for UltraNAND allowing one UltraNAND to be **
** supported on a PC ISA bus. This device includes a RESET input to force **
** WP# asserted on power transitions. RESET is high until Vcc is valid **
** and goes high when supply power ramps down. **
\****************************************************************************/
/** Inputs **/
Pin 1 = !WRITE; /* System Write Enable */
Pin 2 = !READ; /* System Read Enable */
Pin [3..6] = [A0..3]; /* Address input to select port */
Pin 7 = !CE; /* Chip Enable for the interface and UltraNAND */
Pin 8 = RY_BY; /* RY/BY# input from UltraNAND */
Pin 9 = RESET; /* RESET - high for reset and power transitions */
Pin 10 = INIT; /* INIT from the optional Boot Loader PLD */
/** Outputs **/
Pin 23 = READY; /* Allows system to read RY/BY# pin state */
Pin 22 = CLE; /* Command Latch Enable to UltraNAND */
Pin 21 = ALE; /* Address Latch Enable to UltraNAND */
Pin 20 = !SE; /* Spare Area Enable to UltraNAND */
Pin 19 = !WP; /* Write Protect to UltraNAND */
Pin [18..16] = [!OUTCE0..2]; /* Chip Enables to UltraNAND */
Pin 15 = !WE; /* Write Enable to UltraNAND */
Pin 14 = !RE; /* Read Enable to UltraNAND */
/** Declarations and Intermediate Variable Definitions **/
PORT0 = CE & !A3 & !A2 & !A1 & !A0 /* Data read/write port */
# INIT & !A1 & !A0;
PORT1 = CE & !A3 & !A2 & !A1 & A0 /* CLE write port */
# INIT & !A1 & A0;
PORT2 = CE & !A3 & !A2 & A1 & !A0 /* Used to set ALE */
# INIT & A1 & !A0;
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