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| 型號： | 22363A |
| 英文描述： | Simple System Interface for UltraNAND Flash |
| 中文描述： | 簡單的系統(tǒng)接口UltraNAND閃光 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 725K |
| 代理商： | 22363A |
Publication#
22363
Issue Date:
April 20, 1999
Rev:
A
Amendment/
0
Simple System Interface for
UltraNAND Flash
Application Note
AMD has developed the UltraNAND product line to
address high-density non-volatile memory needs. Tar-
get applications include code and data storage in em-
bedded or removable media systems. This application
note describes a simple hardware system interface for
up to three UltraNAND banks, using a single
AmPALLV16V8-10SC or AmPALLV22V10-10PC PLD
(Programmable Logic Device). A bank combines two or
more 8-bit UltraNAND devices to accomodate system
system bus width requirements (16-bit or higher).
Note:
Please refer to the UltraNAND device data sheet and
“Boot Loader for UltraNAND Flash Simple System Interface”
application note for further information as necessary.
Appropriate Applications
AMD’s
Ultra
NAND Flash provides high-speed read,
program, and erase operations at a lower cost per bit
than NOR Flash, which makes it ideal for high-density
non-volatile storage applications. Appropriate applica-
tions are those that use non-volatile memory to store
code or data which is transferred, or shadowed, to a
high-speed memory resource—like synchronous
DRAM—for fast random access or execution.
Ul-
tra
NAND has relatively slow (7
μ
s) access to random
pages, but fast (50 ns) access to sequential bytes
within a selected page. The slow random access and
the requirement for command and address input
makes
Ultra
NAND inappropriate for code XIP (Execute
in Place) operations. The fast sequential read and
write speed, high-density, and lower cost per bit make
Ultra
NAND ideal for disk replacement or other high-vol-
ume non-volatile storage applications that do not re-
quire high-speed random access.
System Related Benefits of UltraNAND
UltraNAND has been designed to be fully hardware
and software compatible with NAND architecture Flash
already available on the market. However, current
competitive products generally require ECC (Error
Check and Correction) to meet their specified program/
erase cycle endurance, and are not typically available
as 100% good devices. Most of these competing de-
vices are sold with the understanding that they may
have a few bad blocks when shipped from the manu-
facturer. Using a product with bad blocks usually re-
quires that the system provide some form of bad block
memory space. The requirement for ECC and bad
block mapping adds hardware and software design
complexity, generally increases total system cost, and
impacts system performance. In some cases the per-
formance impact can be as great as a 40% decrease in
overall data throughput.
UltraNAND has been designed as an improved product
solution over the competition, providing 100,000 pro-
gram/erase cycle endurance without requiring ECC.
UltraNAND is also available with 100% good blocks,
which eliminates the need for bad block mapping. The
program/erase cycle endurance, without ECC, and
availability of 100% good devices greatly simplifies
system design requirements. Applications can use Ul-
traNAND with simple system interface logic, rather
than the sophisticated memory controller that would be
required with competing devices. The package, pin-
out, command set, and bus interface compatibility of
UltraNAND allow applications designed to support
older NAND architecture devices to be simplified, and/
or cost reduced, with UltraNAND.
UltraNAND Interface Requirements
As shown in Figure 1, UltraNAND utilizes a multiplexed
command/address/data bus. All command, address,
and data information is passed to and from the device
through I/O[0..7] (8-bit I/O port). Control signals are
provided on the device for CE# (Chip Enable), CLE
(Command Latch Enable), ALE (Address Latch En-
able), WE# (Write Enable), RE# (Read Enable), SE#
(Spare area Enable), and WP# (Write Protect). There
is also an open drain RY/BY# (Ready/Busy) output pin
used to indicate when the device is busy with an inter-
nal operation.
System applications using UltraNAND must generate
the proper control signals for the device which, in many
cases, are not used by any other system resource.
Fortunately, the interface logic required to generate the
appropriate UltraNAND signals is reasonably simple
and can be designed in discrete logic, incorporated in
a PLD, or included in the system ASIC. The simple
system interface designs included in this application
note have been developed for the AmPALLV16V8 and
AmPALLV22V10 PLDs. Source and simulation code
for two PLD versions, single and multiple bank support,
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